search for: linkfield

Displaying 20 results from an estimated 30 matches for "linkfield".

2012 Oct 19
11
[LLVMdev] Predication on SIMD architectures and LLVM
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2012 Jun 29
2
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
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2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
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2013 Nov 21
1
[LLVMdev] [PATCH] Making Type::getScalarSizeInBits() const
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2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
...for any changes made to this message after it was sent. Please note that Codeplay Software Ltd does not accept any liability or responsibility for viruses and it is your responsibility to scan any attachments. > Company registered in England and Wales, number: 04567874 > Registered office: 81 Linkfield Street, Redhill RH1 6BY > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
2012 Jun 27
3
[LLVMdev] Counting instructions in MCJIT
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2012 Jun 29
0
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
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2012 Jun 29
2
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
...e > to this message after it was sent. Please note that Codeplay Software > Ltd does not accept any liability or responsibility for viruses and it > is your responsibility to scan any attachments. > Company registered in England and Wales, number: 04567874 Registered > office: 81 Linkfield Street, Redhill RH1 6BY > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev _______________________________________________ LLVM Developers mailing...
2012 Jul 02
0
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
...is message after it was sent. Please note that Codeplay Software >> Ltd does not accept any liability or responsibility for viruses and it >> is your responsibility to scan any attachments. >> Company registered in England and Wales, number: 04567874 Registered >> office: 81 Linkfield Street, Redhill RH1 6BY >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________...
2013 May 09
2
[LLVMdev] Scheduling with RAW hazards
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2012 Feb 29
1
[LLVMdev] Restrictions on bitcast of arbitrary vector types?
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2013 Apr 09
0
[LLVMdev] Getting the position of a BasicBlock that doesn't exist anymore in the backend
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2013 Jul 22
0
[LLVMdev] Predication bug in AggressiveAntiDepBreaker?
...bility for any changes made to this message after it was sent. Please note that Codeplay Software Ltd does not accept any liability or responsibility for viruses and it is your responsibility to scan any attachments. Company registered in England and Wales, number: 04567874 Registered office: 81 Linkfield Street, Redhill RH1 6BY -------------- next part -------------- Index: AggressiveAntiDepBreaker.cpp =================================================================== --- AggressiveAntiDepBreaker.cpp (revision 186828) +++ AggressiveAntiDepBreaker.cpp (working copy) @@ -399,7 +399,7 @@ unsigne...
2013 Sep 24
1
[LLVMdev] llvm/clang and 'odd bit types'
Hi all, I recently created a version of llvm/clang for an architecture with some odd properties: - front end side: -- char,short,int : 20 bits -- long, long long: 40 bits -- pointer: 20 bits On the backend side, I have hardware support for 20-bit registers (and load/stores). (So, I have support for 'i20' and 'i40', but 'i40' is lowered into operations on 'i20')
2013 Oct 21
0
[LLVMdev] Instruction Emitter crash when emitting glued InlineAsm SDNode
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2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
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2012 Jun 28
0
[LLVMdev] Counting instructions in MCJIT
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2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
Hi Marcello, On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement branching > on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so I'm > not exactly
2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
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2013 Aug 26
0
[LLVMdev] Question about boolean type variable generation of Global Variable Optimization
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