Displaying 5 results from an estimated 5 matches for "ldwrd".
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ldrd
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...Not coalescable.
64L %vreg6<def> = COPY %vreg4<kill>; DLDREGS:%vreg6,%vreg4
Considering merging %vreg4 with %vreg6 to DLDREGS
RHS = %vreg4 = [48d,64d:0) 0 at 48d
LHS = %vreg6 = [64d,80d:1)[80d,112d:0) 0 at 80d 1 at 64d
updated: 48L %vreg6<def> = LDWRd %vreg5<kill>;
mem:LD2[%a](align=1)(tbaa=!"int") DLDREGS:%vreg6 PTRREGS:%vreg5
Joined. Result = %vreg6 = [48d,80d:1)[80d,112d:0) 0 at 80d 1 at 48d
96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
Not coalescable.
********** INTERVALS POST JOINING *********...
2011 Mar 28
0
[LLVMdev] Possible missed optimization?
...%vreg6<def> = COPY %vreg4<kill>; DLDREGS:%vreg6,%vreg4
> Considering merging %vreg4 with %vreg6 to DLDREGS
> RHS = %vreg4 = [48d,64d:0) 0 at 48d
> LHS = %vreg6 = [64d,80d:1)[80d,112d:0) 0 at 80d 1 at 64d
> updated: 48L %vreg6<def> = LDWRd %vreg5<kill>; mem:LD2[%a](align=1)(tbaa=!"int") DLDREGS:%vreg6 PTRREGS:%vreg5
> Joined. Result = %vreg6 = [48d,80d:1)[80d,112d:0) 0 at 80d 1 at 48d
> 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8
> Not coalescable.
> ********** INTERVALS PO...
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
...o reduce it
to the following C function:
void foo(int *a) // int here is 16bits
{
*a &= 0xFF;
}
This is the code before regalloc:
Live Ins: %R25R24
%vreg0<def> = COPY %R25R24; DREGS:%vreg0
%vreg2<def> = COPY %vreg0; PTRREGS:%vreg2 DREGS:%vreg0
%vreg1<def> = LDWRd %vreg2; mem:LD2[%a](align=1)(tbaa=!"int")
DLDREGS:%vreg1 PTRREGS:%vreg2
%vreg3<def> = ANDIWRdK %vreg1, 255; DLDREGS:%vreg3,%vreg1
%vreg5<def> = COPY %vreg0; PTRREGS:%vreg5 DREGS:%vreg0
STWRr %vreg5, %vreg3<kill>; mem:ST2[%a](align=1)(tbaa=!"int")
PT...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote:
> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS:
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other