search for: ldrd

...ted led to a crash. The issue can't be reproduced when using GCC 4.2. It can't be reproduced with Clang when the optimization is turned off (O0). This issue can be reproduced with Xcode 4.2.1 and Xcode 4.3 Developer Preview 3 (4E71d). The LLVM optimizer coalesces two loads into an ARM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' in...

...> The issue can't be reproduced when using GCC 4.2. It can't be reproduced with Clang when the optimization is turned off (O0). > This issue can be reproduced with Xcode 4.2.1 and Xcode 4.3 Developer Preview 3 (4E71d). > > The LLVM optimizer coalesces two loads into an ARM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' in...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021] (after optimization) %reg1054<def...

...ue can't be reproduced when using GCC 4.2. It can't be reproduced with Clang when the optimization is turned off (O0). >> This issue can be reproduced with Xcode 4.2.1 and Xcode 4.3 Developer Preview 3 (4E71d). >> >> The LLVM optimizer coalesces two loads into an ARM 'ldrd' double-load instruction. Unfortunately, some ARM hardware platforms (including all of Apple's) support misaligned accesses for single-register loads and stores ('ldr' and 'str' instructions), but not for double-register loads and stores ('ldrd' and 'strd' in...

On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021] > > (after...

Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD instruction. Ops.pop_back(); Ops.pop_back(); // Form the pair instruction. if (isLd) { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc)) .addReg(EvenReg, RegStat...

> Note that this code compiled with GCC 4.2 runs perfectly whereas LLVM will produce a binary that crashes: LLVM breaks existing source code. On this point: This is not uncommon - and the very nature of "Undefined Behaviour". This reason alone is not enough to justify a change to Clang. We/you would need to show that the behaviour is defined & Clang is violating that definition.

...ted when required. The patch makes the assumption that any inline asm statement relying on the even/odd allocation will make use of the %Hn syntax to reference the high (odd) register. However, this is not the case. A common pattern where llvm still fails is code using the abbreviated syntax for LDRD and friends supported by gas: __asm__ ("ldrd %0, [%1]" : "=r"(a) : "r"(b)); Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possibl...

On Tue, Jan 24, 2012 at 08:36:17AM -0800, Esperanza de Escobar wrote: > No one is arguing that there aren't ABI specs or LLVM design > guidelines that say that unaligned accesses "should not", "could not" > or "aren't guaranteed to" work, because it's besides the point. No, it is the core of the issue. Standard C gives the compiler certain

...of silicon to support them. With Xcode's switch to LLVM, this deployed silicon has suddenly become off-limits because of a single overzealous optimization. The only possible workarounds are assembly code and turning the optimizer off altogether. It would be one thing if the optimizer generated ldrd/strd for 64-bit loads and stores only. But it actually goes as far as taking two separate 32-bit accesses and merging them into one silently-incompatible 64-bit access. These two accesses could be unrelated to one another in the context of the code at hand, and even syntactically distant. This int...

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be a...

...llgård Cc: LLVM Dev; weimingz at codeaurora.org Subject: Re: Problems with 64-bit register operands of inline asm on ARM On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to ha...

...m body. It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1. This is correct. > So it a constraint is a 64-integer type, it *probably* needs paired GPR. This is not. Consider the Thumb2 encodings of LDRD, LDREXD, etc,, for example. They allow arbitrary Rt and Rt2, not just a register pair. It's only in ARM mode that the instructions are more constrained. -Jim > > Weiming > > > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundati...

...ted when required. The patch makes the assumption that any inline asm statement relying on the even/odd allocation will make use of the %Hn syntax to reference the high (odd) register. However, this is not the case. A common pattern where llvm still fails is code using the abbreviated syntax for LDRD and friends supported by gas: __asm__ ("ldrd %0, [%1]" : "=r"(a) : "r"(b)); Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possibl...

...t apple.com>> wrote: >>> >>> Hi James, >>> >>> I’m not too familiar with Sparc’s design here, but you may find it useful to have a look at how the ARM target deals with this sort of thing. In particular, the load/store optimization pass which can form the LDRD/STRD instructions among other things. >>> >>> -Jim >>> >>>> On Apr 2, 2015, at 11:43 AM, James Y Knight <jyknight at google.com <mailto:jyknight at google.com> <mailto:jyknight at google.com <mailto:jyknight at google.com>>> wrote: &g...

...MachineInstr.h but couldn't find it out. > > You probably want to iterate through the instruction's operands > (MachineInstr::operands_begin/end) looking for defines ("isDef") of > the registers you care about. Some instructions will write multiple > registers (e.g. ldrd), and the information is in a certain sense > approximate (an empty inline asm block may be marked as writing some > registers, but not actually do anything). > > A call instruction "BL" also gets marked with the registers the > function uses for return values so that LLVM...

...our input on. The problem is exemplfied in the codegen for the function @bar in the attached IR file: bar: push {r4, lr} sub sp, #12 (1) movw r2, :lower16:.L_MergedGlobals (1) movt r2, :upper16:.L_MergedGlobals ldm.w r2, {r0, r1, r3, r12, lr} ldrd r4, r2, [r2, #20] strd lr, r4, [sp] str r2, [sp, #8] (2) mov r2, r3 **** mov r3, r12 **** bl baz add sp, #12 pop {r4, pc} The two moves marked with **** are unnecessary. Especially the first, which co...

...I got the following failures in "make check-lit"   LLVM :: CodeGen/ARM/2009-10-27-double-align.ll    LLVM :: CodeGen/ARM/align.ll    LLVM :: CodeGen/ARM/arguments-nosplit-double.ll    LLVM :: CodeGen/ARM/arguments-nosplit-i64.ll    LLVM :: CodeGen/ARM/arguments.ll    LLVM :: CodeGen/ARM/ldrd.ll    LLVM :: CodeGen/ARM/va_arg.ll    LLVM :: CodeGen/Thumb2/thumb2-ldrd.ll Cheers, -- Rafael Ávila de Espíndola

...I reproduce your test case? I tried with r271685 using 'llc -O3 -regalloc=pbqp zia.ll', but I got: bar: .fnstart @ BB#0: .save {r0, r1, r2, r3, r4, lr} push {r0, r1, r2, r3, r4, lr} ldr r0, .LCPI0_0 ldm.w r0, {r1, r2, r3, r12, lr} ldrd r4, r0, [r0, #20] strd lr, r4, [sp] str r0, [sp, #8] mov r0, r1 mov r1, r2 mov r2, r3 mov r3, r12 bl baz pop {r0, r1, r2, r3, r4, pc} .p2align 2 which has even more registers used. Ch...