search for: ldrexd

...(b)); Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Thus I believe the safest solution is to always force 64-bit operands into even/odd pairs for any inline asm. In other words, we should probably...

On 7/16/14, 6:09 PM, sgundapa wrote: > I see a couple of issues here. > > If I include .S files for ARM, the –no-integrated-as path complains about > Assembler errors. > > The integrated-as path works fine though. > These are very likely just differences between the old ARM assembler syntax and the new 'Unified' syntax. Can you use an assembler that accepts UAL

...M Dev; weimingz at codeaurora.org Subject: Re: Problems with 64-bit register operands of inline asm on ARM On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have something bet...

.... It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1. This is correct. > So it a constraint is a 64-integer type, it *probably* needs paired GPR. This is not. Consider the Thumb2 encodings of LDRD, LDREXD, etc,, for example. They allow arbitrary Rt and Rt2, not just a register pair. It's only in ARM mode that the instructions are more constrained. -Jim > > Weiming > > > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation >...

On 13 March 2013 13:43, Måns Rullgård <mans at mansr.com> wrote: > One possible fix, which I have tested, is to look for the specific > instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in > addition to the 'H' modifier. However, there are probably other > creative ways in which inline asm might rely on the specific pairing. > Hi Mans, Either that method is ignoring an inline asm parser or there isn't one, but I agree, we should be able to have some...

Hi, I'm wondering if LLVM plans to support paired register constraints for 64-bit data. Take ARM for example, the atomic i64 value read/write instuctions: ldrexd/strexd, require aligned register pairs (even/odd). Currently, in LLVM ARM (ARMISelDAGToDAG.cpp), ldrexd/strexd get hard coded registers (R0,R1) before register allocation via intrinsic. It would be neater if there is a register constraint and register class that support 64-bit data and let...

...(b)); Here the second destination register is implicitly one higher than the first. Because of this, the %H0 construct is never used, so the forced even/odd allocation is skipped. One possible fix, which I have tested, is to look for the specific instructions requiring such a pair (LDRD/STRD and LDREXD/STREXD) in addition to the 'H' modifier. However, there are probably other creative ways in which inline asm might rely on the specific pairing. Thus I believe the safest solution is to always force 64-bit operands into even/odd pairs for any inline asm. In other words, we should probably...

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See