search for: ld_desc_base

...ctor load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); s...

...(). > I've tried to change mem_msa to hold only let MIOperandInfo = (ops > simm10) but there It sounds like you're on the right track but there may be an easier way. Continuing on this track, I believe you will also need to change the addrimm10 mentioned in the argument list for LD_DESC_BASE. The one for MIPS will be matching the DAG using the selectIntAddrMSA() function which will produce the two operands expected by mem_msa. I haven't tried this but given that you only want an immediate address, it may be easier to use an immediate operand (e.g. uimm4_ptr, you may need to search...

...pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather instructions only for the x86 processor - there, they defined new SDNodes called GatherNode and ScatterNode.) Thank you, Alex

...'t any as far as I know. The closest I can think of is in MSA where you can get a similar effect with a sequence of ld.df's and vshf.df's (or pck*.df's, ilv*.df's, etc. for some of the common cases). > If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather instructions only for the x86 processor - there, they defined new SDNodes called GatherNode and ScatterNode.) > > Thank you, > Alex > _______________________________________________ > LLV...

...a5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather instructions only for the x86 processor - there, they defined new SDNodes called GatherNode and ScatterNode.) Thank you, Alex _______________________________________________ LLVM Developers mailing list llv...

...tter operations exist for Mips, named LVI and SVI, respectively. >> >> Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector >> instructions) gather and scatter operations? >> If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, >> but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather >> instructions only for the x86 processor - there, they defined new SDNodes called >> GatherNode and ScatterNode.) >> >> Thank you, >> Alex >> __________________...

...exist for Mips, named LVI and SVI, respectively. >>> >>> Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector >>> instructions) gather and scatter operations? >>> If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, >>> but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather >>> instructions only for the x86 processor - there, they defined new SDNodes called >>> GatherNode and ScatterNode.) >>> >>> Thank you, >>> Alex &gt...

...named LVI and SVI, respectively. >>>> >>>> Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector >>>> instructions) gather and scatter operations? >>>> If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, >>>> but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather >>>> instructions only for the x86 processor - there, they defined new SDNodes called >>>> GatherNode and ScatterNode.) >>>> >>>> Thank you, &...