Displaying 2 results from an estimated 2 matches for "ld256_n".
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ld256
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
...48(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG)
{
//dont know the details of this part
but here i plan to encode 2048 elements again in 32 v64i32 but with
different instruction name like previously it was
load<LD256; i intend to make it load<LD256_N
so that in instructioninfo.td while pattern matching both LD256 and LD256_N
are treated separately. 1 will use Reg_B registers and other will use Reg_A
respectively.
Is it fine???
Please guide me...
I need serious help, please.....
Thank You
On Mon, Jul 10, 2017 at 9:29 AM, hameeza ahmed <...
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
hello,
i have a situation where i have to assign the registers to instructions
based on the loop iterations.
for eg..
the registers are:
R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,
R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,
R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.
These registers defined in object Reg_A
These are total 12 registers. will use them contiguously, here i define it
in above mentioned order i.e