search for: ld256

Displaying 13 results from an estimated 13 matches for "ld256".

2017 Jul 07
2
Error in v64i32 type in x86 backend
...but the following error on console: > > LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x > i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, > t12, undef:i64 > t7: v64i32 = add t6, t4 > t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x > i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, > undef:i64 > t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x > i32]* @c> 0 > t13: i64 = TargetGlobalAddress<[65 x i32]...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...raph but the following error on console: >> >> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a >> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >> t7: v64i32 = add t6, t4 >> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64 >> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0 >> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0 >&gt...
2017 Jul 06
2
Error in v64i32 type in x86 backend
...combine2-dags i get the required output in graph but the following error on console: LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 t7: v64i32 = add t6, t4 t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64 t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0 t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0 t3: i64 = undef t4: v64i...
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
...ement static SDValue LOAD2048(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG) { //dont know the details of this part but here i plan to encode 2048 elements again in 32 v64i32 but with different instruction name like previously it was load<LD256; i intend to make it load<LD256_N so that in instructioninfo.td while pattern matching both LD256 and LD256_N are treated separately. 1 will use Reg_B registers and other will use Reg_A respectively. Is it fine??? Please guide me... I need serious help, please..... Thank You On Mon, Jul 1...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...>>>> >>>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* >>>> @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >>>> t7: v64i32 = add t6, t4 >>>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >>>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, >>>> undef:i64 >>>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* >>>> @c> 0 >>>> t13:...
2017 Jul 08
2
Error in v64i32 type in x86 backend
...t index 18943, continuing at 19028 Match failed at index 16201 Continuing at 19029 LLVM ERROR: Cannot select: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 t7: v64i32 = add t6, t4 t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)(dereferenceable)> t0, t11, undef:i64 t11: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0 t10: i64 = TargetGlobalAddress<[65 x i32]* @c> 0 t3: i64 = undef t4: v64i...
2017 Jul 08
2
Error in v64i32 type in x86 backend
...ontinuing at 19029 >>>> LLVM ERROR: Cannot select: t9: ch = store<ST256[bitcast ([65 x i32]* @c >>>> to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 >>>> t7: v64i32 = add t6, t4 >>>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >>>> i32>*)](align=16)(tbaa=<0x3817578>)(dereferenceable)> t0, t11, >>>> undef:i64 >>>> t11: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* >>>> @c> 0 >>>> t10:...
2017 Jul 08
5
Error in v64i32 type in x86 backend
...x i32>*)](align=16)(tbaa=<0x3817578>)> t8, >>>>>>>>>>>>>> t7, t11, undef:i64 >>>>>>>>>>>>>> t7: v64i32 = add t6, t4 >>>>>>>>>>>>>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 >>>>>>>>>>>>>> x i32>*)](align=16)(tbaa=<0x3817578>)(dereferenceable)> t0, >>>>>>>>>>>>>> t11, undef:i64 >>>>>>>>>>>>>> t...
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...4 files (2 .td, 1 .h, 1 .cpp), I no longer get this strange error. However, now I start getting Segfault at selection for masked_gather, the reason being that I don't have vector registers of 64-bits: ISEL: Starting pattern match on root node: t14: v128i16,ch = masked_gather<LD256[<unknown>]> t0, t22, t29, TargetConstant:i64<0>, t33 Initial Opcode index to 1692 #0 0x00007f08faa9e700 llvm::sys::PrintStackTrace(llvm::raw_ostream&) /llvm/lib/Support/Unix/Signals.inc:402:0 #1 0x00007f08faa9ea9a PrintStackTraceSignalHan...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2; Unfortunately, now I have another problem: llc fails when trying to select my masked_gather node. More exactly, it first tries to split it and then gives an error: Split node operand: t13: v128i16,ch = masked_gather<LD256[<unknown>]> t0, t23, t40, TargetConstant:i64<0>, t24 Widen node result 0: t46: v64i16 = extract_subvector t23, Constant:i64<64> Widen node result 0: t48: v64i16,ch = masked_gather<LD128[<unknown>](align=256)> t0, t46, t44, TargetConstant:i64<0>, t2...
2017 Feb 11
2
Specify special cases of delay slots in the back end
Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure: