Displaying 8 results from an estimated 8 matches for "ld16".
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ld1
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...ags is
possible, so the Flags should be added to the FoldingSetNodeID.
3) Something else I haven't considered.
I have a patch posted implementing 2, but don't know if I should look
at fixing 1 as well (or perhaps instead). The loads that trigger the
assertion are:
t47: v4i32,ch = load<LD16[%0+80](align=8)(dereferenceable)> t20, t46, undef:i64
t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64
I would expect the the second load should also be marked
dereferenceable since its loading from one of the TargetFrames. Am I
on the right track here?
Thanks
Sean...
2016 Sep 03
4
llc error
...,
The attached LLVM assembly file fails to generate x86 code when compiled
using llc.
compilation command - ../llvm-build/bin/llc -filetype=asm -march=x86-64
-mcpu=core-avx2 ex4.ll
The error message is,
LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16, undef:i64
t16: i64 = add t2, Constant:i64<16>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t1: i64 = Register %vreg5
t15: i64 = Constant<16>
t4: i64 = undef
In function: _ZN10soundtouch12TDStretchSSE13calcCro...
2016 Dec 26
2
[SDAG] Recovering pointer types
...re the
same (i64 according to the DataLayout).
So I end up with this as the initial SDAG:
Initial selection DAG: BB#0 'test:entry'
SelectionDAG has 9 nodes:
t0: ch = EntryToken
t3: i64 = Constant<0>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64
t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5
t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1
What I would like to do is emit efficient code for cases where the
parameter pointer has the same alignment requirements as the load a...
2016 Sep 03
2
llc error
...t;> using llc.
>>
>> compilation command - ../llvm-build/bin/llc -filetype=asm -march=x86-64
>> -mcpu=core-avx2 ex4.ll
>>
>> The error message is,
>>
>> LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
>> t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16,
>> undef:i64
>> t16: i64 = add t2, Constant:i64<16>
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
>> t1: i64 = Register %vreg5
>> t15: i64 = Constant<16>
>> t4: i64 = und...
2016 Dec 26
0
[SDAG] Recovering pointer types
...yout).
>
> So I end up with this as the initial SDAG:
> Initial selection DAG: BB#0 'test:entry'
> SelectionDAG has 9 nodes:
> t0: ch = EntryToken
> t3: i64 = Constant<0>
> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2, undef:i64
> t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5
> t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1
>
> What I would like to do is emit efficient code for cases where the parameter pointer has the same alignment requi...
2016 Mar 15
3
how to type-legalize a dag
...lection DAG: BB#0 'main:entry'
SelectionDAG has 14 nodes:
0x3e7e2f0: ch = EntryToken
0x3ea45e0: i32 = undef
0x3e7e2f0: <multiple use>
0x3ea43d0: i32 = FrameIndex<1>
0x3ea45e0: <multiple use>
0x3ea46e8: v4i32,ch = load 0x3e7e2f0, 0x3ea43d0,
0x3ea45e0<LD16[%a](align=4)> [ORD=5]
0x3e7e2f0: <multiple use>
0x3ea47f0: i32 = FrameIndex<2>
0x3ea45e0: <multiple use>
0x3ea48f8: v4i32,ch = load 0x3e7e2f0, 0x3ea47f0,
0x3ea45e0<LD16[%b](align=4)> [ORD=6]
0x3ea4e20: i32 = Register %R11
0x3ea46e8: <multipl...
2016 Dec 26
2
[SDAG] Recovering pointer types
...with this as the initial SDAG:
> > Initial selection DAG: BB#0 'test:entry'
> > SelectionDAG has 9 nodes:
> > t0: ch = EntryToken
> > t3: i64 = Constant<0>
> > t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> > t5: v4i32,ch = load<LD16[%0](tbaa=<0x10038f18a98>)> t0, t2,
> undef:i64
> > t7: ch,glue = CopyToReg t0, Register:v4i32 %V2, t5
> > t8: ch = PPCISD::RET_FLAG t7, Register:v4i32 %V2, t7:1
> >
> > What I would like to do is emit efficient code for cases where the
> parameter pointer...
2016 Jan 18
3
error of using GATHER intrinsic
...x double> undef)
I could load my pass successfully with opt, but I got the following errors
when I either run the new bitcode using lli or generate the assembly using
llc:
PromoteIntegerOperand Op #2: 0x41bf3a8: v2f64,ch = masked_gather 0x415ec40,
0x41bf030, 0x41bf280, 0x41bbb30, 0x41becb8<LD16[%a]> [ORD=8] [ID=0]
Do not know how to promote this operator's operand!
Any idea about this error? Or could anyone give me an example how to use
the gather intrinsic if there is something wrong with the way I am using it?
Best,
Zhi
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