Displaying 7 results from an estimated 7 matches for "lbzu".
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2012 Sep 19
0
[LLVMdev] "Unknown node flavor ..." Was: Re: tablegen and ptr_rc: PointerLikeRegClass
...can't tell whether or not this is progress.
Using the memri definitions as inspiration:
+def ptr_rc_wrapper : Operand<iPTR> {
+ let PrintMethod = "printMemRegImm";
+ let MIOperandInfo = (ops ptr_rc:$ea_result);
+}
And then swapping out the ptr_rc: references like so:
-def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:
$addr),
+def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_wrapper:$ea_result), (ins
memri:$addr),
"lbzu $rD, $addr", LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result&...
2012 Sep 14
2
[LLVMdev] tablegen and ptr_rc: PointerLikeRegClass
Hi all,
I've been poking at AsmParser support for powerpc64
(ppc64-elf-linux-abi) and have run into some behavior I don't understand
with the ptr_rc references coming out of the PPC*.td files when
generating the asm-matcher files.
For instance :
$ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I
~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/
-gen-asm-matcher
2012 Nov 15
3
[LLVMdev] Tablegen and ptr_rc: PointerLikeRegClass
...>
> Using the memri definitions as inspiration:
> +def ptr_rc_wrapper : Operand<iPTR> {
> + let PrintMethod = "printMemRegImm";
> + let MIOperandInfo = (ops ptr_rc:$ea_result);
> +}
>
> And then swapping out the ptr_rc: references like so:
>
> -def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:
> $addr),
> +def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_wrapper:$ea_result), (ins
> memri:$addr),
> "lbzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<&quo...
2017 May 28
2
Pseudo-instruction that overwrites its input register
On Sun, 28 May 2017, David Chisnall wrote:
>> let Constraints = "@earlyclobber $reg" in
>> def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>> (ins PTRREGS:$ptrreg),
>> "ldw\t$reg, $ptrreg",
>> [(set i16:$reg, (load i16:$ptrreg))]>,
>>
2017 May 30
2
Pseudo-instruction that overwrites its input register
...`NoEncode`. You can see examples of it that are very similar to what you're after in
> PPC's load/store with update forms (i.e. load a value and update the base register
> with the effective address - these are used for pre-increment loads/stores).
> For example: the definition of LBZU and friends in lib/Target/PowerPC/PPCInstrInfo.td.
> For a simpler example of just the `RegConstraint` usage (as it doesn't use a compound
> node like PPC's address nodes), you can look at all the fused multiply-add such as
> XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td.
>
&g...
2011 Jun 02
2
rsync is coring
Greetings!
We are running an rsync process every hour and it is producing a core
file. We thought initially there was a corrupt file but that is gone and
the core file is still being produced. Would appreciate any help in
analysing the core file.
Thanks,
Vincent Soosai
Java Developer
Phone: 503 745 2615
If you are not the intended addressee, please inform us immediately that you have
2017 May 30
1
Pseudo-instruction that overwrites its input register
...that are very similar to what
>> you're after in
>> PPC's load/store with update forms (i.e. load a value and update the base
>> register
>> with the effective address - these are used for pre-increment
>> loads/stores).
>> For example: the definition of LBZU and friends in
>> lib/Target/PowerPC/PPCInstrInfo.td.
>> For a simpler example of just the `RegConstraint` usage (as it doesn't
>> use a compound
>> node like PPC's address nodes), you can look at all the fused
>> multiply-add such as
>> XSMADDADP in lib/...