Displaying 20 results from an estimated 125 matches for "l5".
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2010 Mar 23
1
chan_ss7 issue
...rsion 1.0.95-beta.
I have 8 E1s running on a DL380 server. This enable to have calls from sip
to ss7 and vice versa. However ss7 links are not stable.
linkset siuc, link l1, schannel 1, sls 0, NOT_ALIGNED, rx: 1, tx: 2/4,
sentseq/lastack: 127/127, total 4034145216, 4031118560
linkset siuc, link l5, schannel 1, sls 1, INSERVICE, rx: 5, tx: 3/3,
sentseq/lastack: 95/95, total 4030833616, 4028245568
^[[A[root at localhost ~]# asterisk -rx "ss7 link status"
linkset siuc, link l1, schannel 1, sls 0, NOT_ALIGNED, rx: 2, tx: 4/4,
sentseq/lastack: 127/127, total 4034149872, 4031123216
links...
2013 Nov 06
2
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
...; preds = %entrypoint
br label %L2
L2: ; preds = %L0, %L1
%2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ]
%3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ]
%4 = sdiv i64 %2, 4
%5 = sdiv i64 %3, 4
br label %L5
L3: ; preds = %L3, %L5
%6 = phi i64 [ %15, %L3 ], [ 0, %L5 ]
%7 = mul i64 %19, 4
%8 = add nsw i64 %7, %6
%9 = getelementptr float* %arg5, i64 %8
%10 = load float* %9
%11 = getelementptr float* %arg6, i64 %8
%12 = load float* %11...
2013 Nov 06
0
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
...; preds = %entrypoint
> br label %L2
>
> L2: ; preds = %L0, %L1
> %2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ]
> %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ]
> %4 = sdiv i64 %2, 4
> %5 = sdiv i64 %3, 4
> br label %L5
>
> L3: ; preds = %L3, %L5
> %6 = phi i64 [ %15, %L3 ], [ 0, %L5 ]
> %7 = mul i64 %19, 4
> %8 = add nsw i64 %7, %6
> %9 = getelementptr float* %arg5, i64 %8
> %10 = load float* %9
> %11 = getelementptr float* %arg6, i64 %8...
2013 Nov 06
2
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
...idea why there are still shufflevector, insertelement, *and* bitcast
(!!) etc. instructions left? The original loop is so clean, a textbook
example I'd say. There is no need to shuffle anything.At least I don't
see it.
Frank
vector.ph: ; preds = %L5
%broadcast.splatinsert1 = insertelement <4 x i64> undef, i64 %19, i32 0
%broadcast.splat2 = shufflevector <4 x i64> %broadcast.splatinsert1,
<4 x i64> undef, <4 x i32> zeroinitializer
br label %vector.body
vector.body: ; preds...
2010 Feb 08
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...lt;BB#5>, 1, %ICC<imp-use>; dbg:expr.c:757
Successors according to CFG: BB#5 BB#4
is compiled down to
! BB#7: ! %bb
! in Loop: Header=BB1_2 Depth=2
sethi 1856, %l5
or %g0, 1, %l6
sll %l6, %l3, %l3
or %l5, 1, %l5
and %l3, %l5, %l3
subcc %l3, 0, %l3
bne .LBB1_8
nop
ba .LBB1_68
nop
! BB#8: ! %bb1...
2018 Apr 16
1
NHW Project - quality improvement for -l4,-l5 settings
Hello,
I have improved quality for -l4 and -l5 high compression settings.These
settings are now really better and very competitive, I now prefer them
compared to x265 (HEVC).
Update at: http://nhwcodec.blogspot.com/
I am also working on -l6 quality setting, I can simply increase
quantization for it but I am not totally satisfied with this sol...
2010 Mar 23
0
[asterisk-ss7]Chan_ss7 issue
...ing on a DL380 server with Digium E1 cards ( 4 port cards).
This enable to have calls from sip to ss7 and vice versa. However ss7 links
are not stable.
linkset siuc, link l1, schannel 1, sls 0, NOT_ALIGNED, rx: 1, tx: 2/4,
sentseq/lastack: 127/127, total 4034145216, 4031118560
linkset siuc, link l5, schannel 1, sls 1, INSERVICE, rx: 5, tx: 3/3,
sentseq/lastack: 95/95, total 4030833616, 4028245568
^[[A[root at localhost ~]# asterisk -rx "ss7 link status"
linkset siuc, link l1, schannel 1, sls 0, NOT_ALIGNED, rx: 2, tx: 4/4,
sentseq/lastack: 127/127, total 4034149872, 4031123216
links...
2009 Dec 11
2
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
Hi, Chris
> That is target independent code, so you should not put sparc specific changes there. It sounds like one of the sparc-specific target hooks is wrong.
Since sparc does not provide any hooks for operation of branches (e.g.
AnalyzeBranch and friends) it might be possible that generic codegen
code is broken in absence of these hooks.
--
With best regards, Anton Korobeynikov
Faculty
2010 Aug 02
2
[LLVMdev] indirectbr and phi instructions
Hi,
How does the requirement that phi instructions have one value per
predecessor basic block interact with indirectbr instructions? For
instance, take the following code:
L1:
br i1 %somevalue, label %L2, label %L3
L2:
%ret1 = i8* blockaddress(@myfunction, %L5)
br label %L4
L3:
%ret2 = i8* blockaddress(@myfunction, %L6)
br label %L4
L4:
%ret = phi i8* [%ret1, L2], [%ret2, L3]
indirectbr i8* %ret, [label %L5, label %L6]
L5:
%myval = phi i32 [0, %L2], [1, %L3] ; are both of these values required,
even though the only *real* possible prede...
2008 Jan 15
1
flac default is -l8 (but says -l5)
...804 Jan 7 23:00 a.wav
$ flac -v
flac 1.2.1
$ type flac
flac is hashed (/usr/bin/flac)
$ uname -a
CYGWIN_NT-5.1 DFBJ7M51 1.5.24(0.156/4/2) 2007-01-31 10:57 i686 Cygwin
$ flac -f a.wav
a.wav: wrote 16323314 bytes, ratio=0.534
$ flac -l8 -f a.wav
a.wav: wrote 16323314 bytes, ratio=0.534
$ flac -l5 -f a.wav
a.wav: wrote 16398095 bytes, ratio=0.536
$ flac
...
flac - Command-line FLAC encoder/decoder version 1.2.1
-# is -0 (fastest compression) to -8 (highest compression); -5 is the default
====================================================
a side question is: -l8 is slower to encode but...
2013 Nov 06
0
[LLVMdev] loop vectorizer: Unexpected extract/insertelement
...ll shufflevector, insertelement, *and* bitcast (!!) etc. instructions left? The original loop is so clean, a textbook example I'd say. There is no need to shuffle anything.At least I don't see it.
>
> Frank
>
>
> vector.ph: ; preds = %L5
> %broadcast.splatinsert1 = insertelement <4 x i64> undef, i64 %19, i32 0
> %broadcast.splat2 = shufflevector <4 x i64> %broadcast.splatinsert1, <4 x i64> undef, <4 x i32> zeroinitializer
> br label %vector.body
>
> vector.body:...
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
...%7, 32
%11 = trunc i64 %10 to i32
%12 = getelementptr i32, i32* %arg1, i64 2
%13 = bitcast i32* %12 to i64*
%14 = load i64, i64* %13, align 8
%15 = trunc i64 %14 to i32
%16 = getelementptr i32, i32* %arg1, i64 3
%17 = lshr i64 %14, 32
%18 = trunc i64 %17 to i32
br label %L5
L5: ; preds = %L5, %entrypoint
%19 = phi i64 [ %32, %L5 ], [ %4, %entrypoint ]
%20 = shl i64 %19, 4
%21 = or i64 %20, 4
%22 = or i64 %20, 8
%23 = or i64 %20, 12
%broadcast.splatinsert9 = insertelement <4 x i32> undef, i32 %8, i3...
2010 Feb 08
0
[LLVMdev] How to check for "SPARC code generation" in MachineBasicBlock.cpp?
...an MBB). It
> appears that the branch delay-slots are specifically to blame here
Yes, most certainly.
> - the above BB#315 immediately prior to output is
>
> BB#7: derived from LLVM BB %bb
> Live Ins: %L1 %L0 %L3 %L2 %L4
> Predecessors according to CFG: BB#6
> %L5<def> = SETHIi 1856
> %L6<def> = ORri %G0, 1
> %L3<def> = SLLrr %L6<kill>, %L3<kill>
> %L5<def> = ORri %L5<kill>, 1
> %L3<def> = ANDrr %L3<kill>, %L5<kill>
> %L3<def,dead> = SUBCCri %L...
2018 Apr 28
2
quality improvement of -l4, -l5, -l6 high compression settings
...mmunity!
Cheers,
Raphael
2018-04-28 21:40 GMT+02:00 Dave Johnson Games <davefilms.us at gmail.com>:
> Great news!
>
> On Sat, Apr 28, 2018, 2:10 PM Raphael Canut <nhwcodec at gmail.com> wrote:
>
>> Hello,
>>
>> Great news!!! I have really improved -l4,-l5,-l6 high compression quality
>> settings!
>>
>> The NHW Project is now really competitive, I prefer it to x265 (HEVC) now
>> on many images!
>>
>> Update at: http://nhwcodec.blogspot.com/
>>
>> I don't have touched the entropy coding schemes, and...
2013 Nov 01
2
[LLVMdev] loop vectorizer: this loop is not worth vectorizing
...g0, %arg3
%1 = add nsw i64 %arg1, %arg3
br label %L2
L2: ; preds = %entrypoint, %L0
%2 = phi i64 [ %0, %L0 ], [ %arg0, %entrypoint ]
%3 = phi i64 [ %1, %L0 ], [ %arg1, %entrypoint ]
%4 = sdiv i64 %2, 4
%5 = sdiv i64 %3, 4
br label %L5
L3: ; preds = %L3, %L5
%6 = phi i64 [ %21, %L3 ], [ 0, %L5 ]
%7 = add nsw i64 %26, %6
%8 = add nsw i64 %27, %6
%9 = getelementptr float* %arg5, i64 %7
%10 = load float* %9, align 4
%11 = getelementptr float* %arg5, i64 %8
%12 = loa...
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
...tptr i32, i32* %arg1, i64 2
> %13 = bitcast i32* %12 to i64*
> %14 = load i64, i64* %13, align 8
> %15 = trunc i64 %14 to i32
> %16 = getelementptr i32, i32* %arg1, i64 3
> %17 = lshr i64 %14, 32
> %18 = trunc i64 %17 to i32
> br label %L5
>
> L5: ; preds = %L5,
> %entrypoint
> %19 = phi i64 [ %32, %L5 ], [ %4, %entrypoint ]
> %20 = shl i64 %19, 4
> %21 = or i64 %20, 4
> %22 = or i64 %20, 8
> %23 = or i64 %20, 12
> %br...
2018 Mar 27
0
NHW Project - quality improvement for -l3, -l4, -l5 settings
Hello,
I have improved quality for -l3,-l4,-l5 settings.I have diminished residual
coding and I have raised again quantization.These settings are now better.
Update at: http://nhwcodec.blogspot.com/
The NHW Project with this version starts to be competitive at high
compression with x265.
Any feedback welcome!
Cheers,
Raphael
--------------...
2018 Apr 08
0
NHW Project - quality improvement for -l5 setting
Hello,
Just a quick message to let you know that I have improved the -l5 quality
setting.I have suppressed a data info packet and so I have raised
quantization for this setting.This setting has now more precision and is
better.
Update at: http://nhwcodec.blogspot.com/
I am still working on -l6 and below high compression settings, but it is
not that easy, as I want to...
2018 Apr 28
0
quality improvement of -l4, -l5, -l6 high compression settings
...8-04-28 21:40 GMT+02:00 Dave Johnson Games <davefilms.us at gmail.com>:
>
>> Great news!
>>
>> On Sat, Apr 28, 2018, 2:10 PM Raphael Canut <nhwcodec at gmail.com> wrote:
>>
>>> Hello,
>>>
>>> Great news!!! I have really improved -l4,-l5,-l6 high compression
>>> quality settings!
>>>
>>> The NHW Project is now really competitive, I prefer it to x265 (HEVC)
>>> now on many images!
>>>
>>> Update at: http://nhwcodec.blogspot.com/
>>>
>>> I don't have touched...
2018 Apr 28
0
quality improvement of -l4, -l5, -l6 high compression settings
...mail.com>:
>>>
>>>> Great news!
>>>>
>>>> On Sat, Apr 28, 2018, 2:10 PM Raphael Canut <nhwcodec at gmail.com> wrote:
>>>>
>>>>> Hello,
>>>>>
>>>>> Great news!!! I have really improved -l4,-l5,-l6 high compression
>>>>> quality settings!
>>>>>
>>>>> The NHW Project is now really competitive, I prefer it to x265 (HEVC)
>>>>> now on many images!
>>>>>
>>>>> Update at: http://nhwcodec.blogspot.com/
>...