search for: l2e

...t;) is exactly the same except it is missing one of the predictor variables. What is confusing me is the estimated defrees of freedom for each of the splines in the second model.... ________________ > summary.gam(mod.gam) Family: gaussian Link function: identity Formula: INT ~ s(IGS) + s(L2E) + s(TED) + s(PSD) + s(OPD) + s(GED) Parametric coefficients: Estimate std. err. t ratio Pr(>|t|) constant 302.32 5.192 58.23 < 2.22e-16 Approximate significance of smooth terms: edf chi.sq p-value s(IGS) 4.254 58.308...

...mp; _PAGE_RW) && + !( unlikely(paging_mode_external(d) && (d != curr->domain)) ); + okay = get_data_page(page, d, writeable); if ( !okay ) { MEM_LOG("Error getting mfn %lx (pfn %lx) from L1 entry %" PRIpte @@ -759,11 +782,43 @@ get_page_from_l2e( MEM_LOG("Bad L2 flags %x", l2e_get_flags(l2e) & L2_DISALLOW_MASK); return -EINVAL; } + if ( l2e_get_flags(l2e) & _PAGE_PSE ) + { + unsigned long mfn = l2e_get_pfn(l2e); + unsigned long m, me; + struct page_info *page = mfn_to_page...

...? The 2nd problem I encountered also has to do with walking the shadow page tables to obtain the MFN of the underlying Windows VA address. sh_guest_map_l1e(), Line 520 in the same file, has this code executed after it walks the guest page tables to obtain the walk_t gw variable. if ( gw.l2e && (guest_l2e_get_flags(*gw.l2e) & _PAGE_PRESENT) && !(guest_supports_superpages(v) && (guest_l2e_get_flags(*gw.l2e) & _PAGE_PSE)) ) (XEN) mm.c:2573:d1 grant host mapping: va:81696000 frame:0x15f140 (XEN) mm.c:2507:d1 grant va mapping: va:...

While adding code to create the compatibility p2m table mappings it seemed to me that the creation of the native ones is restricted to memory below the 512G boundary - otherwise, additional L2 tables would need to be allocated (currently other memory following the one L2 page getting allocated would be blindly overwritten). While I realize that machines this big aren''t likely to be

...txt[cpu]) ) - maddr = page_array[maddr >> PAGE_SHIFT] << PAGE_SHIFT; + maddr = (uint64_t)page_array[maddr >> PAGE_SHIFT] << PAGE_SHIFT; return maddr; } @@ -225,7 +222,8 @@ map_domain_va_pae( void *guest_va, int perm) { - unsigned long l3e, l2e, l1e, l2p, l1p, p, va = (unsigned long)guest_va; + uint64_t l3e, l2e, l1e, l2p, l1p, p; + unsigned long va = (unsigned long)guest_va; uint64_t *l3, *l2, *l1; static void *v[MAX_VIRT_CPUS]; @@ -380,12 +378,12 @@ map_domain_va( if (!paging_enabled(&ctxt[cpu])) {...

1: correct LDT checks 2: add address validity check to guest_map_l1e() 3: use {rd,wr}{fs,gs}base when available 4: check for canonical address before doing page walks Signed-off-by: Jan Beulich <jbeulich@suse.com>

...{ According to sp->u.sh.type, (like SH_type_l1_32_shadow ......), get each entry (shadow_l1e_get_flags) of the page table. Changes the flags to read only and then write the page table entry back (shadow_set_l1e). When going through the page table, I can use SHADOW_FOREACH_L1E (L2E, L3E, L4E) macro. However, I have one question. When dealing with shadow page table L2, L3, L4, can I use the same way as L1 page table to change flags and set flags ? } } Do you think my idea is possible? Thanks for giving me some suggestions. Best, Ming

Populate-on-demand: Check pages being returned by the balloon driver This patch series is the second result of my work last summer on decreasing fragmentation of superpages in a guests'' p2m when using populate-on-demand. This patch series is against 4.1; I''m posting it to get feedback on the viability of getting a ported version of this patch into 4.2. As with the previous

...arch/x86/shadow.c 2005-03-10 11:55:10.000000000 +0100 +++ xen/arch/x86/shadow.c 2005-03-14 12:34:26.000000000 +0100 @@ -532,13 +532,15 @@ static void shadow_map_l1_into_current_l { struct exec_domain *ed = current; struct domain *d = ed->domain; - unsigned long *gpl1e, *spl1e, gl2e, sl2e, gl1pfn, sl1mfn, sl1ss; + l1_pgentry_t *gpl1e, *spl1e; + l2_pgentry_t gl2e, sl2e; + unsigned long gl1pfn, sl1mfn, sl1ss; struct pfn_info *sl1mfn_info; int i; __guest_get_l2e(ed, va, &gl2e); - gl1pfn = gl2e >> PAGE_SHIFT; +...

This patch series includes a series of bugs related to p2m, ept, and PoD code which were found as part of our XenServer product testing. Each of these fixes actual bugs, and the 3.4-based version of the patch has been tested thoroughly. (There may be bugs in porting the patches, but most of them are simple enough as to make it unlikely.) Each patch is conceptually independent, so they can each

This patch series restores the use of superpages when restoring or migrating a VM, while retaining efficient batching of 4k pages when superpages are not appropriate or available. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

There has been some progress, but still no joy. Definitely not intended for inclusion at this point. Tim, Wei, I added a Xen command line toggle to disable IOMMU and P2M table sharing. Tim, I verified that changes to p2m-pt.c don''t break shadow mode (64bit hypervisor and Win 7 guest). Hongkaixing, I incorporated your suggestion in patch 2, so I should add your Signed-off-by eventually.

Hi all, this patch series makes the necessary changes to make sure that the current ARM hypercall ABI can be used as-is on 64 bit ARM platforms: - it defines xen_ulong_t as uint64_t on ARM; - it introduces a new macro to handle guest pointers, called XEN_GUEST_HANDLE_PARAM (that has size 4 bytes on aarch and is going to have size 8 bytes on aarch64); - it replaces all the occurrences of

Hi all, this patch series makes the necessary changes to make sure that the current ARM hypercall ABI can be used as-is on 64 bit ARM platforms: - it defines xen_ulong_t as uint64_t on ARM; - it introduces a new macro to handle guest pointers, called XEN_GUEST_HANDLE_PARAM (that has size 4 bytes on aarch and is going to have size 8 bytes on aarch64); - it replaces all the occurrences of

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place