search for: l1p

...ning buffers or prefetch streams. If there multiple such bottlenecks, it would be the minimum of such streams. At the moment I cannot think of an optimization where the difference matters (which doesn't mean there isn't a case where it does). > That seems ok to me. As I understand it, L1P is a little awkward in > that L2 data doesn't get moved to L1P, it gets moved to L1. L1P is > really a prefetch buffer, right? One wouldn't do, say, cache blocking > for L1P. In that sense maybe modeling it as a cache level isn't the > right thing. The L1P (4 KiB) is sma...

...for writing to RAM). Is it the maximum number of operations in the queue? > >> The intent is that getCacheLevel(0) is the L1 cache, getCacheLevel(1) is > >> the L2 cache and so on. > > > > Can passes rely on it? > > Yes. Naively, I'd put Blue Gene/Q's L1P cache between the L1 and the L2, i.e. the L1P would be getCacheLevel(1) and getCacheLevel(2) would be L2. How would you model it instead? Michael

...maddr = page_array[maddr >> PAGE_SHIFT] << PAGE_SHIFT; + maddr = (uint64_t)page_array[maddr >> PAGE_SHIFT] << PAGE_SHIFT; return maddr; } @@ -225,7 +222,8 @@ map_domain_va_pae( void *guest_va, int perm) { - unsigned long l3e, l2e, l1e, l2p, l1p, p, va = (unsigned long)guest_va; + uint64_t l3e, l2e, l1e, l2p, l1p, p; + unsigned long va = (unsigned long)guest_va; uint64_t *l3, *l2, *l1; static void *v[MAX_VIRT_CPUS]; @@ -380,12 +378,12 @@ map_domain_va( if (!paging_enabled(&ctxt[cpu])) { static void * v...

...hers/prefetch instructructions > > for different levels. > > Probably. Most X86 implementations direct all data prefetches to the > same cache level so we didn't find a need to model this, but it makes > sense to allow for it. Again the Blue Gene/Q: Streams prefetch into the L1P cache (P for prefetch), but a dcbt instruction is necessary to establish the cache line into the L1 cache. > >> An open question is how to handle different SKUs within a subtarget > >> family. We modeled the limited number of SKUs used in our products > >> via mult...

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Hi, thank you for sharing the system hierarchy model. IMHO it makes a lot of sense, although I don't know which of today's passes would make use of it. Here are my remarks. I am wondering how one could model the following features using this model, or whether they should be part of a performance model at all: * ARM's big.LITTLE * NUMA hierarchies (are the NUMA domains