Displaying 7 results from an estimated 7 matches for "krzystof".
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krzysztof
2015 Jul 27
1
[LLVMdev] TSFlags
Hi Krzystof,
regarding your first solution (creating separate instruction), is it
possible to somehow have cascading defm?
for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit
condition b, all in one instruction, instead of having one multiclass with
2^5 conditions, is it possible to w...
2017 Jun 14
2
What is HexagonCommonGEP.cpp for?
I only see Hexagon has such optimization, is there any reason that Hexagon
need this?
No existing optimization does similar thing?
Thanks,
Regards,
chenwj
2017-06-14 21:51 GMT+08:00 Krzysztof Parzyszek <kparzysz at codeaurora.org>:
> On 6/14/2017 8:16 AM, 陳韋任 wrote:
>
>> Sounds like you break a single getelementptr into a few smaller ones,
>> then do CSE-like
2017 Jun 14
2
What is HexagonCommonGEP.cpp for?
Krzystof,
Is this partly due to hardware loops not being common? I'm curious, we do
something very similar for similar reasons.
On Wed, Jun 14, 2017 at 10:23 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 6/14/2017 9:05 AM, 陳韋任 wrote:
>
>> I only...
2006 Dec 11
21
iptables 1.3.7, kernel 2.6.19, ROUTE and Layer7 issues
Hi, I''m having problems with this configuration:
iptables 1.3.7 (vanilla or repackaged for fc5)
kernel 2.6.19 (vanilla)
ROUTE 1.11 (last pom-ng)
layer7-filter 2.6 (last in sf.net)
connlimit (last pom-ng)
When I try to use -j ROUTE in any chain in mangle table I have this error:
[root@myhost ~]# iptables -v -t mangle -A POSTROUTING -p tcp --dport msnp
-j ROUTE --gw
2015 Jul 10
0
[LLVMdev] TSFlags
On 7/10/2015 10:23 AM, Sky Flyer wrote:
> Many thanks for your prompt reply.
>
> I mean, imagine you have 3 bits for condition flags in your instruction
> (e.g. overflow, zero, carry set, ...) for conditional executions AND
> there is no direct access to the Status Register, is it even possible to
> implement such scenario?
>
There doesn't have to be any explicit status
2015 Jul 10
3
[LLVMdev] TSFlags
Many thanks for your prompt reply.
I mean, imagine you have 3 bits for condition flags in your instruction
(e.g. overflow, zero, carry set, ...) for conditional executions AND there
is no direct access to the Status Register, is it even possible to
implement such scenario?
On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 7/10/2015 9:32
2015 Aug 12
2
ARM: Predicated returns considered analyzable?
Doh. I missed the list in my first reply... Here's the replay of the
conversation:
----- Renato:
On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR,
> %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>,
>