Displaying 5 results from an estimated 5 matches for "korsa".
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2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
...16 %T_2, %T_1
%tmp1 = mul i16 %tmp, %T_0
%T_11 = sub i16 %T_8, %sum
%T_13 = add i16 %T_11, %tmp1
store volatile i16 %T_13, i16* %O_0
ret void
}
Thanks
On Tue, Sep 30, 2014 at 9:50 PM, Eli Bendersky <eliben at google.com> wrote:
>
>
> On Tue, Sep 30, 2014 at 9:04 AM, RAVI KORSA <ravi.korsa at gmail.com> wrote:
>
>> is there any guarantee that the nvptx intrinsic "llvm.nvvm.barrier0" will
>> not be moved around by opt ?
>> In other words, can I expect all the instructions above
>> "llvm.nvvm.barrier0" to remain above it...
2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
The actual purpose that I wanted such an intrinsic is to solve a problem
similar to this one in X86. Say I wanted to read the "mxcsr" register(which
is the status register for SSE instructions) after a particular
instruction, then I need a kind of barrier intrinsic which will not allow
the arithmetic instructions to move around it. Or else I will be reading
the status of some other
2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
is there any guarantee that the nvptx intrinsic "llvm.nvvm.barrier0" will
not be moved around by opt ?
In other words, can I expect all the instructions above
"llvm.nvvm.barrier0" to remain above it and those below it to remain below,
after all the opt passes are run ?
If that is not the case, is there a way to define such an intrinsic ?
Thanks.
-------------- next part
2014 Feb 26
2
[LLVMdev] How to 'define and use' a LOOP intrinsic that takes "iteration count" and the "label" to jump to ?
I have defined the intrinsic as
* def int_loop: Intrinsic<[],[llvm_i8_ty, llvm_empty_ty],[]>;*
and also got the Codegen backend support in Instructioninfo.td file.
Then created a .ll file to test it.
The .ll file is like this
*declare void @llvm.loop(i8, label)define void @fn() nounwind readnone
{entry: ..... ..... call void @llvm.loop(i8 10, label %entry) ret
void}*
But
2014 Sep 30
2
[LLVMdev] Behaviour of NVPTX intrinsic
...in PTX, can you use inline
> assembly and mark it as having side effects? I think LLVM's optimizer is
> very conservative about inline assembly marked with sideeffect, and will
> probably solve your code motion issue.
>
> Jingyue
>
> On Tue Sep 30 2014 at 11:03:45 AM RAVI KORSA <ravi.korsa at gmail.com> wrote:
>
>> The actual purpose that I wanted such an intrinsic is to solve a problem
>> similar to this one in X86. Say I wanted to read the "mxcsr" register(which
>> is the status register for SSE instructions) after a particular
>...