search for: kevinqindev

...> unless we know we will link std library only at link-time. >> > > If programmers want to do this, they need to compile their program with > -ffreestanding. > > >> >> Thanks, >> -Jiangning >> >> >> 2015-03-31 17:51 GMT+08:00 Kevin Qin <kevinqindev at gmail.com>: >> >>> Yes, I classified `new (std::nothrow)` to be a malloc like allocation. >>> See the next sentence. >>> >>> >>> 2015-03-31 17:48 GMT+08:00 mats petersson <mats at planetcatfish.com>: >>> >>>> > I...

...ial functions, but programmers can still define their own versions by not linking std library, so we must assume malloc/free always have side-effect like other common functions, unless we know we will link std library only at link-time. Thanks, -Jiangning 2015-03-31 17:51 GMT+08:00 Kevin Qin <kevinqindev at gmail.com>: > Yes, I classified `new (std::nothrow)` to be a malloc like allocation. See > the next sentence. > > > 2015-03-31 17:48 GMT+08:00 mats petersson <mats at planetcatfish.com>: > >> > I think we can do such optimization with operator new, because ne...

...ly on the constructor being > called, and the bug here is probably [as I'm not familiar with the > workings of the compiler in enough detail] that it doesn't recognize > that the constructor has side-effects. > > -- > Mats > > On 31 March 2015 at 10:24, Kevin Qin <kevinqindev at gmail.com> wrote: >> Hi, >> >> >> When looking into the bug in https://llvm.org/bugs/show_bug.cgi?id=21421, I >> found a regression test in Transforms/InstCombine/malloc-free-delete.ll >> against me to directly fix it. The test is, >> >> define...

...used for this kind of purpose(though there's also a fixme saying it's hacking). I think it's a good idea to use this pass here. Thanks, Kevin 2015-03-11 17:05 GMT+08:00 Hal Finkel <hfinkel at anl.gov>: > ----- Original Message ----- > > From: "Kevin Qin" <kevinqindev at gmail.com> > > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > > Sent: Wednesday, March 11, 2015 3:47:35 AM > > Subject: [LLVMdev] How to run two loop passes non-interleaved if they > are registered one by one? > > > > > > &...

Hi all, Partial unrolling and runtime unrolling are enabled by default in aarch64 gcc which is help to get performance better. But these two methods are enabled for only several backends in LLVM which are X86, PowerPC and R600. I don't know the history of these two kinds of unrolling, and why they are not widely used. I also want to know is, for aarch64 backend, is it intentionally to get

Hi, When looking into the bug in https://llvm.org/bugs/show_bug.cgi?id=21421, I found a regression test in Transforms/InstCombine/malloc-free-delete.ll against me to directly fix it. The test is, define i1 @foo() { ; CHECK-LABEL: @foo( ; CHECK-NEXT: ret i1 false %m = call i8* @malloc(i32 1) %z = icmp eq i8* %m, null call void @free(i8* %m) ret i1 %z } According to

Hi LLVM developers, I want to add LICM pass after loop unrolling pass in current optimization pipeline. Because both of them are loop passes, so if I registered them one by one, they will interleaved go through all loops in bottom up way within same loop pass manager. Loop unroling pass may create new inner loops from partial unrolling, and those newly created loops can be visited only if the

Hi Tim, 2014-06-25 15:26 GMT+08:00 Tim Northover <t.p.northover at gmail.com>: > Hi Kevin, > > I assume you've looked at the GCC documentation in this area, since > your ideas are very similar: > https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html. I actually > think that looks like a rational set of conventions too. > > The main difference appears to be

On Mon, Aug 11, 2014 at 11:44 PM, Kevin Qin <kevinqindev at gmail.com> wrote: > Hi all, > > Thanks for you paying time to look at this issue. I'm not an expert for > C/C++ language, so I can just post some experiment results from LLVM and > GCC. > > If we make minor changes to the test, gcc may give different results. > &g...

Hi all, Recently, I found gcc can generate faster codes by localizing global variable inside loop and only write back once before function return. Gcc can do this because its alias analysis think it's safe. But for below case, gcc gives different result from -O0 and -O2. #include <stdio.h> struct heap {int index; int b;}; struct heap **ptr; int aa; int main() { struct heap element;

Hi Daniel,    Thank you your replying.     Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported."  Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com

Hi Andrea    Thank you your replying.    I do like your letter. Add following to line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following:

    Thank you Kevin!!!    If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc  double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS.  The command as following: NEON:            vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half

Hi, To fix this bug(http://llvm.org/bugs/show_bug.cgi?id=18881), we need to add more register constraints that for STLXR , Ws and Wt should not be the same register. Because these unpredictable instructions are valid instructions in MC layer, we couldn't just simply treat them as unallocated encoding. I suppose to add some extra rules on register allocator to avoid it allocating register

Hi, Recently, I committed a patch adding default features for '-mcpu'. And after that, Eric replied me here's a proposal toward using '-march' instead of '-mcpu'. As it's half a year later from original proposal, some background may changes. One thing worth to mention is, during this time, Apple Contributed its backend and introduced another new CPU type: cyclone.