search for: kbl

...m repositaries) Wine doesn't work. Neither 1.1.27 (development), nor 1.0.1 (stable). It can't open object files -- there are no such object files. $ winecfg err:module:load_builtin_dll failed to load .so lib for builtin L"winex11.drv": libuuid.so.1: =52>7<>6=> >B:@KBL @0745;O5<K9 >1J5:B=K9 D09;: 5B B0:>3> D09;0 8;8 :0B0;>30 err:module:load_builtin_dll failed to load .so lib for builtin L"winex11.drv": libuuid.so.1: =52>7<>6=> >B:@KBL @0745;O5<K9 >1J5...

..._frontbuffer_tracking: expand badstride and stridechange kms_frontbuffer_tracking: assert the stride changes at stridechange() kms_frontbuffer_tracking: add tilingchange subtest Robert Beckett (1): tests/gem_storedw_loop: Fix use after free for bufmgr Rodrigo Vivi (1): lib/kbl: Add Kabylake PCI IDs Thomas Wood (31): scripts: add quick-testlist.py lib: allow wildcard matching when specifying subtests m4: remove unused macros gem_storedw_loop: fix segfault when listing subtests lib/tests: explicitly raise SIGSEGV lib: add igt_debugfs_se...

...vice-4: Realtek Integrated_Webcam_HD driver: uvcvideo type: USB Display: x11 server: X.Org v: 1.20.11 driver: X: loaded: modesetting dri: iris gpu: i915 resolution: 1: 1920x1080~60Hz 2: 3840x2160~60Hz API: OpenGL v: 4.6 vendor: intel mesa v: 23.3.3 renderer: Mesa Intel UHD Graphics 620 (KBL GT2) The problem is that the external display has some issues, whether they are related to the nouveau driver, the Mate Desktop or something else I cannot determine. What happens is that although the external monitor is indeed using the 1920 x 1080 resolution and dragging a window from the laptop...

...to D1/D2/D3hot before putting the client into D3cold via + * platform means (generally ACPI). + * + * skipping this makes runpm work perfectly fine on such devices. + * + * As far as we know only skylake and kaby lake SoCs are affected. + */ +static unsigned short intel_broken_d3_bridges[] = { + /* kbl */ + 0x1901, +}; + +static inline bool intel_broken_pci_pm(struct pci_bus *bus) +{ + struct pci_dev *bridge; + int i; + + if (!bus || !bus->self) + return false; + + bridge = bus->self; + if (bridge->vendor != PCI_VENDOR_ID_INTEL) + return false; + + for (i = 0; i < ARRAY_SIZE(intel_b...

...don't have anything against this patch, as long as the quirk stays > > limited to the particular root port leading to the NVIDIA GPU. The > > reason why I think it should to be limited is that I'm pretty certain > > the problem is not in the root port itself. I have here a KBL based > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > (it is connected to PCH root port) and it wakes up there just fine, so > > don't want to break that. > > > > Now, PCIe devices cannot go into D3cold all by themselves. They always...

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 libdrm 2.4.84 has been released. Alex Deucher (1): tests/amdgpu: add missing header to SOURCES Andrey Grodzovsky (1): amdgpu: Add deadlock detection test suit. Anuj Phogat (1): intel: Change a KBL pci id to GT2 from GT1.5 Christian König (1): amdgpu: make userptr unit test more interesting Dave Airlie (1): headers: sync syncobj ioctl defines. Eric Engestrom (1): freedreno/kgsl: fix pointer-to-int cast James Zhu (2): tests/amdgpu: add new uvd enc support check...

...dgpu-symbols-check radeon: Pass radeon_bo_open flags to the DRM_RADEON_GEM_CREATE ioctl Rob Clark (4): freedreno: update uapi freedreno: small refactor for get_param freedreno: add support for FD_MAX_FREQ Bump version for release Rodrigo Vivi (1): intel/kbl: Add Kabylake PCI ids Stefan Agner (2): kmstest: Use util_open() tests: add fsl-dcu-drm to modules Sumit Semwal (1): android: enable building static version of libdrm Thierry Reding (1): tests: util: Fixup util_open() parameter order Ville Syrjälä (1):...

...r. > > I don't have anything against this patch, as long as the quirk stays > limited to the particular root port leading to the NVIDIA GPU. The > reason why I think it should to be limited is that I'm pretty certain > the problem is not in the root port itself. I have here a KBL based > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > (it is connected to PCH root port) and it wakes up there just fine, so > don't want to break that. > > Now, PCIe devices cannot go into D3cold all by themselves. They always > need help from the p...

...anything against this patch, as long as the quirk stays > > > limited to the particular root port leading to the NVIDIA GPU. The > > > reason why I think it should to be limited is that I'm pretty certain > > > the problem is not in the root port itself. I have here a KBL based > > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > > (it is connected to PCH root port) and it wakes up there just fine, so > > > don't want to break that. > > > > > > Now, PCIe devices cannot go into D3cold all by...

...me delay like the ones Mika is adding to the reset paths? > + * > + * skipping this makes runpm work perfectly fine on such devices. > + * > + * As far as we know only skylake and kaby lake SoCs are affected. > + */ > +static unsigned short intel_broken_d3_bridges[] = { > + /* kbl */ > + 0x1901, > +}; > + > +static inline bool intel_broken_pci_pm(struct pci_bus *bus) > +{ > + struct pci_dev *bridge; > + int i; > + > + if (!bus || !bus->self) > + return false; > + > + bridge = bus->self; > + if (bridge->vendor != PCI_VENDOR_ID_...

...for the vc4 driver. (Maxime Ripard) - The project has now finalized its name change and is now IGT GPU Tools, docs and install paths are now "igt-gpu-tools". (Arkadiusz Hiler) - Added a blacklist for the Intel CI. (Petri Latvala) Library changes: - i915_pciids.h updated to include KBL, ICL, WHL and AML. (José Roberto de Souza, Paulo Zanoni) - Overhaul of gpu_cmds, gpgpu_fill, media_fill and rendercopy. (Katarzyna Dec, Lukasz Kalamarz) - Added igt_matrix and igt_color_encoding helper libraries. (Ville Syrjälä) - IGT now shows the kernel stack trace when reporting a GPU han...

...o debug this > further. I don't have anything against this patch, as long as the quirk stays limited to the particular root port leading to the NVIDIA GPU. The reason why I think it should to be limited is that I'm pretty certain the problem is not in the root port itself. I have here a KBL based Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold (it is connected to PCH root port) and it wakes up there just fine, so don't want to break that. Now, PCIe devices cannot go into D3cold all by themselves. They always need help from the platform side which is ACPI in...

...t this patch, as long as the quirk stays > > > > limited to the particular root port leading to the NVIDIA GPU. The > > > > reason why I think it should to be limited is that I'm pretty certain > > > > the problem is not in the root port itself. I have here a KBL based > > > > Thinkpad X1 Carbon 6th gen that can put the TBT controller into D3cold > > > > (it is connected to PCH root port) and it wakes up there just fine, so > > > > don't want to break that. > > > > > > > > Now, PCIe devices can...

...ce detected again) > > + * > > + * skipping this makes runpm work perfectly fine on such devices. > > + * > > + * As far as we know only skylake and kaby lake SoCs are affected. > > + */ > > +static unsigned short intel_broken_d3_bridges[] = { > > + /* kbl */ > > + 0x1901, > > +}; > > + > > +static inline bool intel_broken_pci_pm(struct pci_bus *bus) > > +{ > > + struct pci_dev *bridge; > > + int i; > > + > > + if (!bus || !bus->self) > > + return false; > &...

On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas <helgaas at kernel.org> wrote: > > [+cc Dave] > > On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol Herbst wrote: > > Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device > > states. > > > > v2: convert to pci_dev quirk > > put a proper technical explanation of the issue as a

...NVIDIA GTX 1660 Ti. Ken Thomases (1): winemac: Fix failure to render OpenGL on macOS 10.14 (Mojave). Kristj?n Gerhardsson (3): wined3d: Add GPU information for various Mac GPUs. wined3d: Add GPU information for AMD VEGA20. wined3d: Add GPU information for a few more Intel KBL GPUs. Louis Lenders (2): dwmapi: Return DWM_E_COMPOSITIONDISABLED instead of E_NOTIMPL in DwmGetTransportAttributes. gdiplus: Add version resource. Martin Liska (1): include: Avoid compound literals for WCHAR strings. Michael M?ller (5): avifil32: Correctly handle compres...

...ate() (Coverity). winevulkan: Pull in bitmask dependencies for function parameters. Kai Krakow (1): wined3d: Add GPU information for NVIDIA GTX 1660 Ti. Kristján Gerhardsson (2): wined3d: Add GPU information for AMD VEGA20. wined3d: Add GPU information for a few more Intel KBL GPUs. Matteo Bruni (9): d3dx9: Get rid of unused unlock_surface() argument. d3dx9/tests: Make the pixels array static. d3dcompiler/tests: Get rid of redundant "failed" in test strings. d3dcompiler/tests: Trace the test index in test_fail() checks. wined3d: F...

...1 MSI_NB MEGABOOK 01072009 AMI 00010013) [ 0.000000] ACPI: SSDT 0x000000007A8BE2D0 003154 (v02 SaSsdt SaSsdt 00003000 INTL 20160422) [ 0.000000] ACPI: SSDT 0x000000007A8C1428 00287B (v02 PegSsd PegSsdt 00001000 INTL 20160422) [ 0.000000] ACPI: HPET 0x000000007A8C3CA8 000038 (v01 INTEL KBL 00000001 MSFT 0000005F) [ 0.000000] ACPI: SSDT 0x000000007A8C3CE0 000E3B (v02 INTEL Ther_Rvp 00001000 INTL 20160422) [ 0.000000] ACPI: UEFI 0x000000007A8C4B20 000042 (v01 INTEL EDK2 00000002 01000013) [ 0.000000] ACPI: SSDT 0x000000007A8C4B68 000EDE (v02 CpuRef CpuSsdt 000...

...n. lib/cnl: Add Cannonlake PCI IDs for U-skus. lib/cnl: Add Cannonlake PCI IDs for Y-skus. lib/instdone: Add Gen10 support. lib/intel_batchbuffer: Add Gen10 support for render_copy and gpgpu_fillfunc. lib/i915_pciids.h: Organize cnl/cfl ids. i915_pciids: Change a KBL pci id to GT2 from GT1.5 Tvrtko Ursulin (7): igt: Remove default from the engine list gem_exec_basic: Exercise the default engine selection gem_sync: Add all and store_all subtests extended.testlist: Remove some test-subtest combinations igt_core: Skip sync when listi...

Hi Bjorn, I was playing around with some older information again (write into the PCI config to put the card into d3 state). And there is something which made me very curious: If I put the card manually into any other state besides D0 via the 0x64 pci config register, the card just dies and pci core seems to expect this to not happen. pci_raw_set_power_state has this