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...; mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...ram starts by API. For example: SetConstantValue( 5, Vector4( 1, 2, 3, 4 ); // C5 = <1,2,3,4> HANDLE handle = LoadCodeFromFile( filename ); SetCode( handle ); // C5 is referenced here Execute(); -- Tzu-Chien Chiu, 3D Graphics Hardware Enginner, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...a, // 30 CMPfrrrr, // 31 Somewhere in my code, I have to write: unsigned opcode = MI->getOpcode(); // MachineInstr* if (CMPfaaaa == opcode || CMPfaaar == opcode || CMPfaara == opcode || ... -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

...rary) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...ill Wendling <isanbard at gmail.com> wrote: > Frequently releasing software can be a good thing. Especially when it > gets to a point where you have a stable CVS version and many new > features/bug fixes. > -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

.../llvm.org/ > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

...hile (I != MBB.end()) MBB.remove(I++); // **** Q: Doesn't it invalidate the pointers in 'S' ?? **** vector<MachineInstr*>::iterator I = S.begin(); S.end() != I; ++ I) { MBB.push_back(*I); } } -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

...threaded. What is the subject I should use to continue a pre-existing thread? dependence analyzer for machine code? Re: dependence analyzer for machine code? [LLVMdev] Re: dependence analyzer for machine code? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...ights, coalesce virtual registers and remove identity moves but the data structure LiveVariables::VirtRegInfo is _not_ updated. That is, VarInfo::DefInstr may point to an invalid (being coalesced) instruction. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...../llvm/lib/CodeGen/LiveIntervalAnalysis.h" or point my project include path to "llvm/lib/CodeGen" (I use Visual Studio). Why LiveIntervalAnalysis.h is not in "include/llvm/CodeGen" ? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > In my ISA, some registers are write-only. These registers serve as > output ports, writing to these registers will output the values to an > external device. They cannot be read. So their live intervals should > not be joined with any other registers. Ok. Since they are not really registers in the sense that LLVM is used to, I

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

...erClass defined for each instruction operand, but actually the destition operand could be 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'. -- Tzu-Chien Chiu http://www.csie.nctu.edu.tw/~jwchiu/

...;t have to convert your entire .td file(s) over to a > complete set of permutations immediately. > > Good luck, > -- > Misha Brukman :: http://misha.brukman.net :: http://llvm.cs.uiuc.edu > -- Tzu-Chien Chiu, 3D Graphics Hardware Enginner, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...sing dedicated instruction to manipulate the vectors. 2. Support writemask and swizzle (permuate) as part of the instruction syntax. I worked on the backend and don't have much experience on the fronted. Thank you all. -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

...es include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris > > -- > http://nondot.org/sabre/ > http://llvm.org/ > -- Tzu-Chien Chiu, 3D Graphics Hardware Enginner, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...ave now is only iburg, though robust but with very limited functionality. i have consider using "nova" - http://cocom.sourceforge.net/nona.html but it seems not be updated since 2001. any other suggestion? -- Tzu-Chien Chiu, Computer Graphics Guy, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...+10+200); // only TempReg can be allocated }]; } def IntegerRC : RegisterClass<packed, 128, [I0, I1, ..., I100]>; And linearly assigning the read-only registers for each definition of them? -- Tzu-Chien Chiu, 3D Graphics Hardware Enginner, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...n from void function How to define a function with multiple return values? The code: uint, uint, ubyte, uint %main() { ret uint 1, uint 2, ubyte 3, uint 4 } cannot be correctly assembled by llvm-as. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...// <-- add this one? There are four register allocation passes in CodeGen, but I don't know which one will be used unitl run-time (the register allocator is chosen by a command line argument). -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>