search for: jmp_4

...eFunction::iterator i = MF.begin(); i != MF.end(); ++i) origBB.push_back(i); for(unsigned int i = 0; i < origBB.size(); ++i) origBB.at(i)->moveAfter(newEntry); MCInstrInfo tii = *MF.getTarget().getInstrInfo(); MachineInstr *plop = BuildMI(MF, DebugLoc(),tii.get(X86::JMP_4)).addMBB(origBB.at(1)); newEntry->push_back(plop); return false; } And here is the resulting code (it's a simple program with some 'if'): (null) BB#4 JMP_4 <BB#0> if.end BB#3 %RDI<def> = LEA64r %RIP, 1, %noreg, <ga:@.str2>, %noreg ADJCALLSTACKDOWN64 0, %R...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...d(), db, TII->get(X86::MOV32mi)) .addReg(reg).addImm(1).addReg(0).addImm(0).addReg(0) .addImm(0); // Increment loop variable and jmp BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), reg).addReg(reg).addImm(8); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Erase intrinsic MI->eraseFromParent(); MBB->getParent()->dump(); return MBB_cond; } Here is the dump of the original function before my custom inserter (it's basically a main function with a printf and a return inside it): # Machine code for function main: SSA...

...*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)).addReg(regB).addImm(1).addReg(0).addImm(0).addReg(0).addImm(0); BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::ADD64ri32), regC).addReg(regB).addImm(8); BuildMI(*MBB_cond, MBB_erase->end(), db, TII->get(X86::JMP_4)).addMBB(MBB_cond); // Erase intrinsic MI->eraseFromParent(); MBB->getParent()->dump(); return MBB_erase; } I run it on this sample code: #include <stdio.h> int main(int argc, char **argv) { printf("MAIN\n"); return 0; } And it generate this X86 ass...

On Fri, 2015-02-20 at 13:47 -0500, Rafael Espíndola wrote: > > Your task, should you choose to accept it, is to make it cope with other > > forms of relaxation where necessary. > > And if not, please open a bug :-) http://llvm.org/bugs/show_bug.cgi?id=22662 FWIW I could reproduce the 'movl foo, %ebx' one but a relative jump *was* using 16 bits (although gas uses 8):

...AGS<imp-def>; GR64:%vreg6 > %vreg9<def> = COPY %vreg6; GR64:%vreg9,%vreg6 > %vreg10<def> = COPY %vreg4; GR64:%vreg10,%vreg4 > %vreg11<def> = COPY %vreg5; GR64:%vreg11,%vreg5 > JNE_4 <BB#2>, %EFLAGS<imp-use,kill> > JMP_4 <BB#3> > Successors according to CFG: BB#3(4) BB#2(124) > > BB#3: derived from LLVM BB %while.end > Predecessors according to CFG: BB#0 BB#2 > Successors according to CFG: BB#4 > > BB#4: derived from LLVM BB %while.end > Predecessors according to CFG: BB#...

...; Successors according to CFG: BB#2 BB#3 BB#2: derived from LLVM BB %entry Predecessors according to CFG: BB#1 MOV32mi %vreg8, 1, %noreg, 0, %noreg, 0; GR64:%vreg8 %vreg9<def,tied1> = ADD64ri32 %vreg8<tied0>, 8, %EFLAGS<imp-def>; GR64:%vreg9,%vreg8 JMP_4 <BB#1> Successors according to CFG: BB#1 BB#3 BB#3: derived from LLVM BB %entry Predecessors according to CFG: BB#1 BB#2 %EAX<def> = COPY %vreg4; GR32:%vreg4 RETQ %EAX<imp-use> # End machine code for function main. Cheers On 12/09/2014 08:01 PM, Quentin...

I met with the Propeller team today (we work for the same company but it was my first time meeting two members on the team:) ). One thing I have been reassured: * There is no general disassembly work. General disassembly work would assuredly frighten off developers. (Inherently unreliable, memory usage heavy and difficult to deal with CFI, debug information, etc) Minimal amount of plumbing work