Displaying 8 results from an estimated 8 matches for "jmp_1".
2018 Sep 11
2
linear-scan RA
...ormation, you can perform experiments like this (I'm using a NOOP instruction with an implicit use operand to produce some artificial uses).
>
> $ cat test.mir
> name: somefunc
> body: |
> bb.0:
> %0:gr32 = MOV32ri 42
> JB_1 %bb.2, undef implicit $eflags
> JMP_1 %bb.2
>
> bb.1:
> %1:gr32 = MOV32ri 17
> JMP_1 %bb.3
>
> bb.2:
> NOOP implicit %0
> %1 = COPY %0
> JMP_1 %bb.3
>
> bb.3:
> NOOP implicit %1
>
>
>
> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> **...
2018 Sep 11
2
linear-scan RA
...his (I'm using a NOOP instruction with an implicit use
> operand to produce some artificial uses).
> >
> > $ cat test.mir
> > name: somefunc
> > body: |
> > bb.0:
> > %0:gr32 = MOV32ri 42
> > JB_1 %bb.2, undef implicit $eflags
> > JMP_1 %bb.2
> >
> > bb.1:
> > %1:gr32 = MOV32ri 17
> > JMP_1 %bb.3
> >
> > bb.2:
> > NOOP implicit %0
> > %1 = COPY %0
> > JMP_1 %bb.3
> >
> > bb.3:
> > NOOP implicit %1
> >
> >
> >
>...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2018 Sep 11
2
linear-scan RA
...to produce some artificial uses).
> >> >
> >> > $ cat test.mir
> >> > name: somefunc
> >> > body: |
> >> > bb.0:
> >> > %0:gr32 = MOV32ri 42
> >> > JB_1 %bb.2, undef implicit $eflags
> >> > JMP_1 %bb.2
> >> >
> >> > bb.1:
> >> > %1:gr32 = MOV32ri 17
> >> > JMP_1 %bb.3
> >> >
> >> > bb.2:
> >> > NOOP implicit %0
> >> > %1 = COPY %0
> >> > JMP_1 %bb.3
> >&g...
2018 Sep 11
2
linear-scan RA
...;>>>
>>>>>> $ cat test.mir
>>>>>> name: somefunc
>>>>>> body: |
>>>>>> bb.0:
>>>>>> %0:gr32 = MOV32ri 42
>>>>>> JB_1 %bb.2, undef implicit $eflags
>>>>>> JMP_1 %bb.2
>>>>>>
>>>>>> bb.1:
>>>>>> %1:gr32 = MOV32ri 17
>>>>>> JMP_1 %bb.3
>>>>>>
>>>>>> bb.2:
>>>>>> NOOP implicit %0
>>>>>> %1 = COPY %0
&g...
2016 Jun 22
2
x86: How to Force 2-byte `jmp` instruction in lowering
...eamer->EmitCodeAlignment(4);
auto Target = OutContext.createLinkerPrivateTempSymbol();
// Use a two-byte `jmp`. This version of JMP takes an 8-bit relative
offset as
// an operand (computed as an offset from the jmp instruction).
OutStreamer->EmitInstruction(
MCInstBuilder(X86::JMP_1)
.addExpr(MCSymbolRefExpr::create(Target, OutContext)),
getSubtargetInfo());
EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
OutStreamer->EmitLabel(Target);
Which turns into:
.Lxray_sled_0:
.palign 2, 0x90
jmp .Ltmp0
nopw 512(%rax,%rax,1)
.Ltmp...
2019 Sep 27
2
What about multiple MachineMemOperands in one MI (BranchFolding/MachineInstr::mayAlias)?
...chineMemOperands?
(I've tried to find information but could not find any clear definition.)
For example BranchFolder may do things like this (also see https://godbolt.org/z/iphFH4):
# *** IR Dump Before Control Flow Optimizer ***:
bb.0.entry:
...
JCC_1 %bb.2, 5, implicit killed $eflags
JMP_1 %bb.1
bb.1.s1:
CALL64pcrel32 @bar, ... , implicit-def $rax
MOV16mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $bx :: (store 2 into %ir.r)
JMP_1 %bb.3
bb.2.s2:
CALL64pcrel32 @bar, ... , implicit-def $rax
MOV16mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $bx :: (sto...
2020 Feb 28
5
A Propeller link (similar to a Thin Link as used by ThinLTO)?
I met with the Propeller team today (we work for the same company but it
was my first time meeting two members on the team:) ).
One thing I have been reassured:
* There is no general disassembly work. General
disassembly work would assuredly frighten off developers. (Inherently
unreliable, memory usage heavy and difficult to deal with CFI, debug
information, etc)
Minimal amount of plumbing work