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On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>&...

Jeff Bush <jeffbush001 at gmail.com> writes: > Ah, I think I get it now. This was mentioned earlier in the thread, > but it didn't click at the time. It sounds like I can do instruction > selection with a pattern like (omitting selection of the sources): > > let Constraints = "$dst = $oldvalu...

...[(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1, v16i32:$src2), v16i32:$oldvalue))]>; } That's actually pretty clean. Thanks On Thu, May 9, 2013 at 2:15 PM, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > > On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > >> On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >>> Jeff Bush <jeffbush001 at gmail.com> writes: >>> >>>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>>> %ty = select %mask, %y, <0.0, 0.0...

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on wheth...

On Fri, May 10, 2013 at 9:53 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints...

I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the

On May 10, 2013, at 11:53 AM, dag at cray.com wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constrain...

On Wed, May 8, 2013 at 11:32 AM, Nadav Rotem <nrotem at apple.com> wrote: >...we do need support for masked load/stores, and > I think that we should implement them as target independent intrinsics. As I understand, one of the tricks for converting to SSA form in LLVM is to make all variable references be loads/stores, then use Mem2Reg to convert those back to registers. It seems

I'm trying to create a TableGen pattern to match extract_vector_elt. My pattern looks like this: (set i32:$dest, (extract_vector_elt v16i32:$src, i32:$index)) However, when I compile, I get an error: error: Variable not defined: 'extract_vector_elt' However, if I omit the rule and attempt to compile something that uses this functionality with clang, I get this error, which

When LLVM does a comparison of two vectors, in this case with 16 elements, the returned type of setcc is v16i1. The architecture I'm targeting allows storing the result of a vector comparison as a bit mask in a scalar register, but I'm having trouble converting the result of setcc into a value that is usable there. For example, if I try to AND together masks that are the results of two

On May 8, 2013, at 11:07 AM, dag at cray.com wrote: > It might be as simple as adding > an IR-level predicated load and predicated store, I'm not sure. I think that selects on the inputs+outputs of instructions is a good abstraction, and I don't think that we need to add a mask operand to every LLVM IR instruction. However, we do need support for masked load/stores, and I think

Jeff Bush <jeffbush001 at gmail.com> writes: > I'm trying to understand how predicated/masked instructions can be > generated in llvm, specifically an instruction where a set bit in the > mask will write the new result into the corresponding vector lane in > the destination and a clear bit will cause...

I'm having trouble getting TableGen to generate disassembler code. The issue is that I have several TableGen definitions that emit the same instruction encoding. This results in TableGen complaining about encoding conflicts (and not handling those instructions). For example, general purpose registers in the architecture I'm targeting can hold floating point or integer values. As such, I

I'm targeting a custom instruction set that supports predication for all vector operations, but uses general purpose scalar registers to store predicate values (vector comparisons results are also stored as a bit mask in a scalar register). I've currently specified that scalar registers can be either of type v16i1 (for predicates; vectors have 16 elements) or i32, which would allow them