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...tter could get the job done. Isn’t that the job of the code emitter converting the MachineInstruction to machine code through the tableGen which has the definition of each instruction. Isn’t it possible to just activate the code emitter during Post-RA scheduler. Sorry for the trouble! Thanks, Jafar J. From: Jim Grosbach Sent: Thursday, May 30, 2013 9:18 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands sh...

On May 30, 2013, at 11:35 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hi Jim, > > The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two conse...

...ter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitter during post-ra would solve my problem if that’s even possible. Thanks, - Jafar J. From: Jim Grosbach Sent: Thursday, May 30, 2013 8:49 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. Thanks, that helps. The code emitter is definitely not the way you want to go about solving this problem, though. Are the inst...

Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands should have all the semantic information you need without ever looking at the actual encoding. -Jim On May 30, 2013, at 11:08 AM, Jafar J <pluck90 at hotmail.com> wrote: >...

...xactly is write a scheduler which tries to minimize the switching activity between the scheduled instructions in each basic block. One way to do that is by representing each instruction with its complete binary encoding, which will be available after the register allocation. Thanks for the reply! -Jafar J From: Jim Grosbach Sent: Thursday, May 30, 2013 7:55 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at...

...ou want to go about solving this problem, though. Are the instruction opcode (MachineInstr::getOpcode()) and the operand values not sufficient? All the information present in the encoding should be inferable from those, as that’s where the encoding comes from. -Jim On May 30, 2013, at 10:12 AM, Jafar J <pluck90 at hotmail.com> wrote: > I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching act...

...tDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here. Thanks, Jafar J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130530/0dbbadc6/attachment.html>

What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hello, > > Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/li...

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

...and whether it could be called for both x86 and MIPS ? The second question, is it possible to get the complete binary representation of some instruction (<= 32-bit binary encoding) for both x86 and MIPS in post register allocation instruction scheduler, and if yes how is that done ? Thanks, Jafar Jamal. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130226/47b7a99b/attachment.html>

...is ADDiu rt, rs, immediate. The encoding for the instruction is 001001 rs rt immediate, with lengths of 6, 5, 5, 16 respectively. My question is how to map the operands with their right register? i.e. %A1 = rt, %ZERO = rs, and immediate = 30. Sorry if I didn’t make myself clear enough. Thanks, Jafar J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130402/d94d4269/attachment.html>

Hello, Is it possible to pass the two parameters -march=arm and –mcpu=cortex-a5 to llc through DragonEgg’s –fplugin-arg-dragonegg-llvm-option in order to produce an ARM object file? Thanks, Jafar J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130814/ff5ce014/attachment.html>

...about this subject on the dev-list but they didn’t help me with everything, so If it’s not any trouble could you be specific on how to do that, I’m kind of new to using linux environment. If it makes any different I’m using Ubuntu 10.10. Thanks in advance. I appreciate the help. Regards, - Jafar Jamal. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130122/655d677a/attachment.html>

Hi guys Has anyone have any workarounds with Internet Explorer 6 not displaying the mailbox on Outlook Web Access properly? My specs: Wine 0.9 on FC4, IE6 installed using ies4linux The problems (as I can see): the right-click context menu on the mailbox doesn't work (it doesn't display anything) and the compose email interface is missing the place where you can actually type your mail

Hi, I purchashed a Telular Phonecell Fixed Cellular Terminal. I hooked it up to my wildcard fxo card. I can receive calls and these calls are passed on to the Asterisk Calling Card application. My problem is that i can't get DTMF to work properly. If a pin number is 484443543639 i get 4844444333544336639. how can i sort out this problem. Please would like ur urgent assistance.

hi all. was having problems with my phonecell connected to wildcard fxo port. i get problems with detecting DTMF. i have tried relaxDTMF but to no avail. i have asked this before but would like possible causes. is it to do with echo? problems with the GSM network? haven't updated my asterisk for a long time. could this be a problem that has been sorted out. please would appreciate ur input

Hi gang I am running Fedora Core 4 (kernel 2.6.15-1.1831_FC4) and Wine version 0.97 REL 3.fc4 from the Extras repo. Before the update, accessing my mailbox (Outlook Web Access) using IE under Wine works fine, but now, Internet Explorer would crash just after logging in. I have noted this is also happening on my other computers running the same operating system and same version of Wine (again,