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The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: Consider this (valid code): --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2: successors: %bb.3 PS_storerhabs 0, undef %r0 J2_j...

I've looked into that and it's not going to be simple, unfortunately. Here's the original example again: --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2: successors: %bb.3 PS_storerhabs 0, undef %r0 J2_j...

...tes that such merging is legal, however doing so can actually generate wrong code: >> >> Consider this (valid code): >> >> --- >> name: fred >> tracksRegLiveness: true >> >> body: | >> bb.0: >> successors: %bb.1, %bb.2 >> J2_jumpt undef %p0, %bb.2, implicit-def %pc >> J2_jump %bb.1, implicit-def %pc >> >> bb.1: >> successors: %bb.3 >> %r0 = L2_loadruh_io undef %r0, 0 >> PS_storerhabs 0, killed %r0 >> J2_jump %bb.3, implicit-def %pc >> >> bb...

...ve looked into that and it's not going to be simple, unfortunately. >> >> Here's the original example again: >> >> --- >> name: fred >> tracksRegLiveness: true >> >> body: | >> bb.0: >> successors: %bb.1, %bb.2 >> J2_jumpt undef %p0, %bb.2, implicit-def %pc >> J2_jump %bb.1, implicit-def %pc >> >> bb.1: >> successors: %bb.3 >> %r0 = L2_loadruh_io undef %r0, 0 >> PS_storerhabs 0, killed %r0 >> J2_jump %bb.3, implicit-def %pc >> >> bb...

...ined in BB#1. Both definitions can reach the use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs > > BB#0: >     Live Ins: %P0 >         %R0<def> = IMPLICIT_DEF >         J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional branch to BB#2 >     Successors according to CFG: BB#1 BB#2 > > BB#1: >     Predecessors according to CFG: BB#0 >         %R0<def> = IMPLICIT_DEF >     Successors according to CFG: BB#2 > > BB#2: >     Live...

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but

...n BB#1. Both definitions can reach the use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, > NoVRegs > > BB#0: >     Live Ins: %P0 >         %R0<def> = IMPLICIT_DEF >         J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional branch to > BB#2 >     Successors according to CFG: BB#1 BB#2 > > BB#1: >     Predecessors according to CFG: BB#0 >         %R0<def> = IMPLICIT_DEF >     Successors according to CFG: BB#2 > > BB#2: >  ...

...> *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, > NoVRegs > > BB#0: >       Live Ins: %P0 >           %R0<def> = IMPLICIT_DEF >           J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional > branch to > BB#2 >       Successors according to CFG: BB#1 BB#2 > > BB#1: >       Predecessors according to CFG: BB#0 >           %R0<def> = IMPLICIT_DEF >...

...izations >>> # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, >>> NoVRegs >>> >>> BB#0: >>> Live Ins: %P0 >>> %R0<def> = IMPLICIT_DEF >>> J2_jumpt %P0, <BB#2>, %PC<imp-def> ; Conditional >>> branch to >>> BB#2 >>> Successors according to CFG: BB#1 BB#2 >>> >>> BB#1: >>> Predecessors according to CFG: BB#0 >>>...