Displaying 6 results from an estimated 6 matches for "j2_jump".
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
I've looked into that and it's not going to be simple, unfortunately.
Here's the original example again:
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
J2_jumpt undef %p0, %bb.2, implicit-def %pc
J2_jump %bb.1, implicit-def %pc
bb.1:
successors: %bb.3
%r0 = L2_loadruh_io undef %r0, 0
PS_storerhabs 0, killed %r0
J2_jump %bb.3, implicit-def %pc
bb.2:
successors: %bb.3
PS_storerhabs 0, undef %r0
J2_...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
...ve looked into that and it's not going to be simple, unfortunately.
>>
>> Here's the original example again:
>>
>> ---
>> name: fred
>> tracksRegLiveness: true
>>
>> body: |
>> bb.0:
>> successors: %bb.1, %bb.2
>> J2_jumpt undef %p0, %bb.2, implicit-def %pc
>> J2_jump %bb.1, implicit-def %pc
>>
>> bb.1:
>> successors: %bb.3
>> %r0 = L2_loadruh_io undef %r0, 0
>> PS_storerhabs 0, killed %r0
>> J2_jump %bb.3, implicit-def %pc
>>
>> b...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
...tes that such merging is legal, however doing so can actually generate wrong code:
>>
>> Consider this (valid code):
>>
>> ---
>> name: fred
>> tracksRegLiveness: true
>>
>> body: |
>> bb.0:
>> successors: %bb.1, %bb.2
>> J2_jumpt undef %p0, %bb.2, implicit-def %pc
>> J2_jump %bb.1, implicit-def %pc
>>
>> bb.1:
>> successors: %bb.3
>> %r0 = L2_loadruh_io undef %r0, 0
>> PS_storerhabs 0, killed %r0
>> J2_jump %bb.3, implicit-def %pc
>>
>> b...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
The comment in test/CodeGen/X86/branchfolding-undef.mir states that such
merging is legal, however doing so can actually generate wrong code:
Consider this (valid code):
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
J2_jumpt undef %p0, %bb.2, implicit-def %pc
J2_jump %bb.1, implicit-def %pc
bb.1:
successors: %bb.3
%r0 = L2_loadruh_io undef %r0, 0
PS_storerhabs 0, killed %r0
J2_jump %bb.3, implicit-def %pc
bb.2:
successors: %bb.3
PS_storerhabs 0, undef %r0
J2_...
2019 Jun 30
6
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ise a hardware loop pattern, resulting in sub-optimal code, specially compared with what LLVM 7.0 produces.
The code (excerpt) just before the Hexagon Hardware Loops pass on LLVM 9 is this:
bb.5:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%8:intregs = A2_tfrsi -100
J2_jump %bb.3, implicit-def $pc
bb.3.while.body:
; predecessors: %bb.3, %bb.5
successors: %bb.4(0x04000000), %bb.3(0x7c000000); %bb.4(3.12%), %bb.3(96.88%)
%0:intregs = PHI %8:intregs, %bb.5, %3:intregs, %bb.3
%1:intregs = PHI %7:intregs, %bb.5, %5:intregs, %bb.3
%2:intregs = PHI %6:intregs, %bb....
2019 Jul 01
0
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ise a hardware loop pattern, resulting in sub-optimal code, specially compared with what LLVM 7.0 produces.
The code (excerpt) just before the Hexagon Hardware Loops pass on LLVM 9 is this:
bb.5:
; predecessors: %bb.1
successors: %bb.3(0x80000000); %bb.3(100.00%)
%8:intregs = A2_tfrsi -100
J2_jump %bb.3, implicit-def $pc
bb.3.while.body:
; predecessors: %bb.3, %bb.5
successors: %bb.4(0x04000000), %bb.3(0x7c000000); %bb.4(3.12%), %bb.3(96.88%)
%0:intregs = PHI %8:intregs, %bb.5, %3:intregs, %bb.3
%1:intregs = PHI %7:intregs, %bb.5, %5:intregs, %bb.3
%2:intregs = PHI %6:intregs, %bb...