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...mp_packed - sse 1 & 2 compare packed instructions > multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, > Operand CC, Intrinsic Int, string asm, > string asm_alt, Domain d, > OpndItins itins = SSE_ALU_F32P> { > def rri : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, > [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], > itins.rr, d>, > Sched<[WriteFAdd]>; > d...

...1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; Okay, so rA, rS, and rB are register operands. The TableGen classes are defined as: 315 class XForm_base_r3xo_swapped 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<5> A; 320 bits<5> RST; 321 bits<5> B; 322 323 bit RC = 0; // set by isDOT 324 325 let Inst{6-10} = RST; 326 let Inst{11-15} = A; 327 let Inst{16-20} = B; 328 let Inst{21-30} = xo; 329 l...

...ister is in is just: r%4 Which brings me to tablegen: We've got this in our specialized ArchInstrInfo.td: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (outs info.regClass:$r1), (ins info.regClass:$r2, info.regClass:$r3), instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr, [(set info.regClass:$r1, (opNode info.regClass:$r2, info.regClass:$r3))], itin > { le...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

...> > Okay, so rA, rS, and rB are register operands. > > > > The TableGen classes are defined as: > > > > 315 class XForm_base_r3xo_swapped > > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string > asmstr, > > 317 InstrItinClass itin> > > 318 : I<opcode, OOL, IOL, asmstr, itin> { > > 319 bits<5> A; > > 320 bits<5> RST; > > 321 bits<5> B; > > 322 > > 323 bit RC = 0; // set by isDOT > > > > 324 > > 325 let Inst{6-10} = RST;...

...List, I.InOperandList >> >> But instead, I must back substitute what I know the values of these are. >> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) >> >> >> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >> InstrItinClass itin> : >> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, >> CPU16Regs:$ry), >> !strconcat(asmstr, "\t$rz, $rx, $ry"), >> pattern, itin>; >> >> class ArithLogicR16<FRRR16_ins I,...

...(and GPRC:$rS, GPRC:$rB))]>; > > Okay, so rA, rS, and rB are register operands. > > The TableGen classes are defined as: > > 315 class XForm_base_r3xo_swapped > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, > 317 InstrItinClass itin> > 318 : I<opcode, OOL, IOL, asmstr, itin> { > 319 bits<5> A; > 320 bits<5> RST; > 321 bits<5> B; > 322 > 323 bit RC = 0; // set by isDOT > > 324 > 325 let Inst{6-10} = RST; > 326 let Inst{11-15} = A; > 327 l...

...nd rB are register operands. >> > >> > The TableGen classes are defined as: >> > >> > 315 class XForm_base_r3xo_swapped >> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string >> asmstr, >> > 317 InstrItinClass itin> >> > 318 : I<opcode, OOL, IOL, asmstr, itin> { >> > 319 bits<5> A; >> > 320 bits<5> RST; >> > 321 bits<5> B; >> > 322 >> > 323 bit RC = 0; // set by isDOT >> > >> > 324 >&gt...

class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure wh...

...PC/PPCInstrFormats.td (revision 54985) > +++ lib/Target/PowerPC/PPCInstrFormats.td (working copy) > @@ -309,6 +309,17 @@ > let Inst{31} = 0; > } > > +class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, > + string asmstr, InstrItinClass itin, list<dag> pattern> > + : I<opcode, OOL, IOL, asmstr, itin> { > + let Pattern = pattern; > + let Inst{6-10} = 0; > + let Inst{11-15} = 0; > + let Inst{16-20} = 0; > + let Inst{21-30} = xo; > + let Inst{31} = 0; > +} > + > class XFo...

...> > > Okay, so rA, rS, and rB are register operands. > > > > The TableGen classes are defined as: > > > > 315 class XForm_base_r3xo_swapped > > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, > > 317 InstrItinClass itin> > > 318 : I<opcode, OOL, IOL, asmstr, itin> { > > 319 bits<5> A; > > 320 bits<5> RST; > > 321 bits<5> B; > > 322 > > 323 bit RC = 0; // set by isDOT > > > > 324 > > 325 let Inst{6-10} = RST;...

...tor instructions for the Mips back end): class MSA_I16_FMT<bits<9> opcode>: MSAInst { bits<16> s16; let Inst{31-23} = opcode; let Inst{26-11} = s16; } class REP_1R_DESC_BASE<, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); /* From include/llvm/Target/Target.td: let OperandType = "OPERAND_IMMEDIATE" in { ... def i64imm : Operand<i64>; */ dag InOperandList = (ins i64imm...

...lem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), !strconcat(asmstr, "\t$rz, $rx, $ry"), pattern, itin>; class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: FRRR16<I.f, (ou...

...gt;> > The TableGen classes are defined as: > >> > > >> > 315 class XForm_base_r3xo_swapped > >> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, > >> > string > >> asmstr, > >> > 317 InstrItinClass itin> > >> > 318 : I<opcode, OOL, IOL, asmstr, itin> { > >> > 319 bits<5> A; > >> > 320 bits<5> RST; > >> > 321 bits<5> B; > >> > 322 > >> > 323 bit RC = 0; // set by isDOT > >...

...<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with the operaand lists not working if there is substitution required. Tablegen is only complaining about $rx, $ry an...

...============== --- lib/Target/PowerPC/PPCInstrFormats.td (revision 54985) +++ lib/Target/PowerPC/PPCInstrFormats.td (working copy) @@ -309,6 +309,17 @@ let Inst{31} = 0; } +class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { + let Pattern = pattern; + let Inst{6-10} = 0; + let Inst{11-15} = 0; + let Inst{16-20} = 0; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + class XForm_25<bits<6> opcode, bits<10> xo,...

...Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); string AsmString = !strconcat("mov $wd, ($addrsrc)"); list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))]; InstrItinClass Itinerary = itin...

...[SDTCisInt<0>, SDTCisSameAs<0, 1>]>; def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, [SDNPOutGlue]>; class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, RegisterClass RC, list<Register> DefRegs>: FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), !strconcat(instr_asm, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin> { let rd = 0; let shamt = 0; let Defs = DefRegs; } Note:,there doesn...

...PU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what I did originally should have worked and the bug was > correct as I reported it. > > Here is an alternate implementation which has the same problem....

...replacing the MachineOperand flags in the R600 backend with immediate operands, but I can't figure out how to modify the instruction patterns to make this work. For example, I have the class: class R600_1OP <bits<32> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : InstR600 <inst, (outs R600_Reg32:$dst), (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags), !strconcat(opName, " $dst, $src ($p)"), pattern, itin >; And an instruction def: def CEIL : R600_1OP < 0x...