search for: isvirtualregist

...run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp: unsigned regA = mi->getOperand(0).getReg(); unsigned regB = mi->getOperand(1).getReg(); assert(MRegisterInfo::isVirtualRegister(regA) && MRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); By machine code I meant code with virtual registers, instead of machine (physical) registers; not the passes on machine functions/machin...

.../ weights, coalesce virtual registers and remove identity moves ... for (unsigned i = 0; i < mii->getNumOperands(); ++i) { const MachineOperand& mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isD...

...t TargetRegisterClass *RC = &LASER::GNPRegsRegClass; unsigned Reg = RegInfo.createVirtualRegister(RC); But then I get the following error: MachineCopyPropagation.cpp:267: void anonymous}::MachineCopyPropagation::CopyPropagateBlock(llvm::MachineBasicBlock&): Assertion `!TargetRegisterInfo::isVirtualRegister(Reg) && "MachineCopyPropagation should be run after register allocation!"' failed. How can I solve my problem of getting two free registers in eliminateFrameIndex() ? Thank you, Ehsan Ali.

...ser->getOpcode() == ISD::CopyToReg &&              User->getOperand(2).getNode() == Node &&              User->getOperand(2).getResNo() == i) {            unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();            if (TargetRegisterInfo::isVirtualRegister(Reg)) { -            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); -            if (RegRC == RC) { +            // Allow constraining the virtual register's class within reason, +            // just like what AddRegisterOperand will allow. +            const TargetRegisterClas...

...copies from virtual registers, which don't behave // like other nodes from the perspective of scheduling heuristics. - if (SDNode *N = SU->getNode()) + if (SDNode *N = PredSU->getNode()) if (N->getOpcode() == ISD::CopyFromReg && TargetRegisterInfo::isVirtualRegister (cast<RegisterSDNode>(N->getOperand(1))->getReg())) ~ -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130821/721dc102/attachment.html>

...ual registers and remove identity moves > > ... > for (unsigned i = 0; i < mii->getNumOperands(); ++i) { > const MachineOperand& mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > > LiveInterval &RegInt = getInterval(reg); > RegInt.weight += >...

On 08/09/05, Chris Lattner <sabre at nondot.org> wrote: > This code isn't actually replacing the virtual register with a physreg. Then why changing its optype? It makes the assertion fails: MachineOperand& MO = inst.getOperand(n); if (MRegisterInfo::isVirtualRegister(MO.getReg())) { assert(MachineOperand::MO_VirtualRegister == MO.getType()); ... } Is that alright? Some of my code using MachineOperand::getType() instead of MRegisterInfo::is{Physical,Virtual}Register() to check the register type. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <UR...

...was thinking that it only transformed instructions with virtual > registers because of this code in the TwoAddressInstructionPass.cpp: > > unsigned regA = mi->getOperand(0).getReg(); > unsigned regB = mi->getOperand(1).getReg(); > > assert(MRegisterInfo::isVirtualRegister(regA) && > MRegisterInfo::isVirtualRegister(regB) && > "cannot update physical register live information"); > > By machine code I meant code with virtual registers, instead of machine > (physical) registers; not the passes on ma...

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: > Thank you Chris. I will try to implement the TwoAddress pass to run on > machine code. Why it has not been originally implemented to run on > machine code? I'm not sure what you mean. It definitely does run on machine code. > Is there anything that makes it troublesome after RA > has been performed? Do you

...bi != mbbe; ++mbbi ) { for( opi = 0, ope = mbbi->getNumOperands(); opi < ope; ++opi ) { MachineOperand & operand = mbbi->getOperand(opi); if( operand.isReg() == false ) continue; if( operand.getReg() == 0 ) continue; if( ! TargetRegisterInfo::isVirtualRegister(operand.getReg()) ) continue; if( mbb != operand.getNextOperandForReg()->getParent()->getParent() ) liveout.push_back( operand.getReg() ); } } return liveout; } On Fri, Nov 5, 2010 at 7:41 AM, s Last namerc <srcsrc84 at yahoo.com> wrote: > Is there...

...akob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg) == REG_Y)) { LiveInterval &LI = LIS->getInterval(VirtReg); unassign(LI, REG_Y); enqueue(&LI); } } RegClassInfo.runOnMachineFunction(VRM->getMachineFunction()); // update reserve reglist So similar to...

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

Thank you Chris. I will try to implement the TwoAddress pass to run on machine code. Why it has not been originally implemented to run on machine code? Is there anything that makes it troublesome after RA has been performed? Could you tell me if the transformations below are correct? 1) a := b op c --> a := b --> a := b a := a op c a

...as a 00188 // stack slot or remat id. 00189 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG); 00190 } VRM::assignVirt2Phys is implemented as: 00147 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { 00148 assert(TargetRegisterInfo::isVirtualRegister(virtReg) && 00149 TargetRegisterInfo::isPhysicalRegister(physReg)); 00150 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && 00151 "attempt to assign physical register to already mapped " 00152 "virtual register"); 00153...

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

...rand(0).getReg(); // A sub-register definition can only be rematerialized if the instruction // doesn't read the other parts of the register. Otherwise it is really a // read-modify-write operation on the full virtual register which cannot be // moved safely. if (TargetRegisterInfo::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg)) return false; // Avoid instructions obviously unsafe for remat. if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects()) return false; // Don't remat inline asm....

...(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { [...] for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->getOperand(i).setReg(reg); Doesn't that last statement actually do the rewrite? And how does this interact with the spill cost computation? I'm t...

...needs one /// physical register. std::set<unsigned> seen_regs; for(unsigned u = 0; u < mi->getNumOperands(); u++) { const MachineOperand & mo = mi->getOperand(u); if(mo.isUse() && mo.isRegister() && mo.getReg()) { if(MRegisterInfo::isVirtualRegister(mo.getReg())) { unsigned v_reg = mo.getReg(); if(this->vrm->hasStackSlot(v_reg)) { int slot = this->vrm->getStackSlot(v_reg); // First, try to fold the memory reference into the // instruction. If we can do this, we don't nee...

...ssigned Reg " << MRI->getName(PReg) << "\n"); for (LiveIntervals::const_iterator K = LIs->begin(); K != LIs->end(); ++K) { const LiveInterval& L = K->second; unsigned LIReg = L.reg; if (!MRegisterInfo::isVirtualRegister(LIReg) || LIReg == VReg) continue; // **** Check to see if the physreg we assigned conflicts with something // **** else. If so, that thing has to live in memory too. if (VRM->hasPhys(LIReg) && VRM->getPhys(LIReg) == PReg && !VRM->hasStackSlo...

...wing piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): > > for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) > && (VRM->getPhys(VirtReg) == REG_Y)) > { > LiveInterval &LI = LIS->getInterval(VirtReg); > unassign(LI, REG_Y); > enqueue(&LI); > } > } > RegClassInfo.runOnMachineFunction(VRM->getMachineFunction());...