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Hi I''m trying to monitor my multi ISP shorewall with swping, the script works fine, i can see in log when an ISP is down, the script restart shorewall and /etc/shorewall/isusable is called, however in the swping log after the shorewall restart i see again a route by ISP (even the ISP down), is it normal ? should i not see one route less? shorewall version 4.4.5.4-1. ****

[Splitting this out from the original thread to reduce noise in it] On 17.06.2013, at 18:43, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 17, 2013, at 7:03 AM, Benjamin Kramer <benny.kra at gmail.com> wrote: > >> >> On 17.06.2013, at 15:56, Diego Novillo <dnovillo at google.com> wrote: >> >>> On 2013-06-15 16:39 ,

On Jun 17, 2013, at 10:48 AM, Benjamin Kramer <benny.kra at gmail.com> wrote: > [Splitting this out from the original thread to reduce noise in it] > > > On 17.06.2013, at 18:43, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> +LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { >> + return (isDef + isUse) * freq.getFrequency();

Kalle: Your patch is similar to what I'd coded (and am testing, which means a couple of hours before I consider committing). Other than cosmetic changes and changing 'NULL' to '0' (it's an integer list, after all). This patch now causes new problems in the CellSPU backend (more stqd's and lqd's), so I have to investigate those before committing the patch.

On Jun 17, 2013, at 7:03 AM, Benjamin Kramer <benny.kra at gmail.com> wrote: > > On 17.06.2013, at 15:56, Diego Novillo <dnovillo at google.com> wrote: > >> On 2013-06-15 16:39 , Benjamin Kramer wrote: >>> Do you want to take over this effort or should I poke more at it? >> >> Since you've already started, it's easier if you poke more at

On 17.06.2013, at 15:56, Diego Novillo <dnovillo at google.com> wrote: > On 2013-06-15 16:39 , Benjamin Kramer wrote: >> Do you want to take over this effort or should I poke more at it? > > Since you've already started, it's easier if you poke more at it. Thanks. I've got a whole bunch of other things to go through. OK, will do. Jakob any comments on the

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; }

Hello http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1536 "Integer underflow in the file_printf function in the "file" program before 4.20 allows user-assisted attackers to execute arbitrary code via a file that triggers a heap-based buffer overflow." Is FreeBSD 5.x/6.x affected too? It looks the System has file 4.12. The port has 4.20. Regards, Thomas -- Terry

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

Ugh. Management lobotomy kicked in. Need to RTFC better. On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs =

On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Ok. > > I tried to do it using a pass after register allocation, lowering NEG/ABS instructions. > However I met a problem : apparently getNextOperandForReg() can returns a MachineOperand before the one I'm processing. > > The following code snippet : > > > void

...:59 thebighonker dovecot: imap(ler): Panic: file > imap-sieve-storage.c: line 616: unreached > > I can provide more logs, but doing the same to (one of) the base > mailbox(es) does NOT garner > the message. > > > 600 can_discard = FALSE; > 601 switch (isuser->cur_cmd) { > 602 case IMAP_SIEVE_CMD_APPEND: > 603 cause = "APPEND"; > 604 can_discard = TRUE; > 605 break; > 606 case IMAP_SIEVE_CMD_COPY: > 607 case IMAP_SIEVE_CMD_MOVE:...

Hey, guys, could someone tell me some high level things about the version of linear scan that you use? 1) The heuristics for spilling seems to be: (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth besides not spilling defs that are immediatly followed by uses, do you do any other thing, such as, taking into consideration the size of the interval when spilling? 2) How do you

I'm doing the delay slot optimization for MIPS and I've noticed that two other ports that are doing this have to work around a problem in the instruction abstraction. Would be nice to fix this and not propagate the hack. The basic problem is that on a call, you want to get the set of explicit and implicit operands but NOT the variable operands. There is no way do this without

...nder Cygwin on Windows Server 2003 (SP1) with Apache 2.0. The Rails apps works fine when proxied through Apache and running under WebRick, but Mongrel seems unhappy about something. The Apache service is running as the "Local System" user and I''m starting Mongrel as "ISUser" which is an Active Directory user. When I invoke the following command: mongrel_rails start -h It returns the following error message: /usr/lib/ruby/gems/1.8/gems/mongrel-1.0.1-mswin32/lib/http11.so: Permission denied - /usr/lib/ruby/gems/1.8/gems/mongrel-1.0.1-mswin32/ lib/http11.so...

In LiveVariables.cpp, when traversing the instructions, all defs of registers are initially marked as kills. See the code around the comment "Defaults to dead". Then later on, when a pass changes instructions, the LiveVariables code updates the kills lists, but it only does so for uses, not defs. See the code around the comment "If this is a kill of the value, update the VI kills

Hi all, I am attempting to implement the "reaching definitions" data-flow algorithm on (X86) MachineBasicBlocks for an analysis pass. To do this, I need to compute gen/kill sets for machine basic blocks. To start with, I am only considering the general-purpose registers, RAX-R15 and their sub-registers. Thus, I need to examine each MachineInstr to determine which register(s) it

On Feb 28, 2010, at 11:49 PM, <Kalle.Raiskila at nokia.com> <Kalle.Raiskila at nokia.com> wrote: > Jakob Stoklund Olesen skrev: >> On Feb 26, 2010, at 10:09 AM, Scott Michel wrote: >>> This patch now causes new problems in the CellSPU >>> backend (more stqd's and lqd's), so I have to investigate those >>> before committing the patch. >

Do you know any backend that implement instructions as a flag modifier in instruction ? Thank, Vincent Lejeune ----- Mail original ----- > De : Jakob Stoklund Olesen <stoklund at 2pi.dk> > À : Vincent Lejeune <vljn at ovi.com> > Cc : "llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)" <llvmdev at cs.uiuc.edu> > Envoyé le : Lundi 6 août 2012 20h06 >

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some