search for: istwoaddrress

...ry complex. I just wonder if LLVM already supports something like this in any form. 3) My target has only 2 addr instructions, i.e. each instruction has at most 2 operands. Do I still need to use 3 operands for such operations like OR, AND, ADD, SUB in my instruction descriptions, but mark them as isTwoAddrress=1??? Or do I need to call a special pass that converts everything into 2-operand instructions? 4) Following Chris advice regarding multiclasses, I defined several multiclasses, each containing 6 defs. But I noticed that I cannot use "let isTwoAddress=1" or "let isCommutable=1"...

...mplement a register allocator that is specific to this problem. > 3) My target has only 2 addr instructions, i.e. each instruction has at > most 2 operands. Do I still need to use 3 operands for such operations > like OR, AND, ADD, SUB in my instruction descriptions, but mark them as > isTwoAddrress=1??? Or do I need to call a special pass that converts > everything into 2-operand instructions? Using isTwoAddrress=1 should do it. > Thanks, > Roman Best Regards, Rafael

On Mon, 2 Oct 2006, Roman Levenstein wrote: >>> Wouldn't it be possible and even more clean to have just one >>> description like (I use a pseudo-description here): >>> >>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst, >>> (i8mem|i16mem|i32mem):$src), >>> "mov{b} {$src, $dst|$dst, $src}", []>,

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",