search for: isrs

It''s everytime when cpufreq_ondemand or cpufreq-set changes the frequency, aprox. 3 messages per event. Is that occasional? I tend to say: no. Please see an excerpt below. And if it''s not occasional, what could I do? And by the way: I found no code that TSC will get adjusted, so I think it will get worse over the time... Thanks, Carsten. messages.0:Jan 9 12:25:15 data kernel:

Up front I apologize for the lengthy email. Since our patch was not accepted, Chris asked us to follow up with this issue on llvm-dev. For the sake of completeness, let me give a bit of background and the problems that we are facing. I tried to capture as much as possible here so Please do give us feedback. Don't take your stack for granted.... PIC16 has very poor pointer handling, hence

MSIX spec requires that device can be operated with all vectors masked, by polling. So the following patchset (lightly tested) adds this ability: when driver reads ISR, the device recalls a pending notification, and returns pending status in the ISR register. The polling driver can operate as follows: - map all VQs and config to the same vector - poll ISR to get status - this also flushes VQ

MSIX spec requires that device can be operated with all vectors masked, by polling. So the following patchset (lightly tested) adds this ability: when driver reads ISR, the device recalls a pending notification, and returns pending status in the ISR register. The polling driver can operate as follows: - map all VQs and config to the same vector - poll ISR to get status - this also flushes VQ

The behaviour of default ISRs as provided by the BIOS varies wildly between platforms. Some will simply iret, some will send EOI, some will send EOI and disable the interrupt at the PIC, some will crash the machine due to single-bit errors in the ISR address. When PXENV_UNDI_ISR_IN_START returns PXENV_UNDI_ISR_OUT_NOT_OURS, s...

Hi Ali, Thanks for bringing this up. You're definitely under very tight design constraints from the hardware. I can certainly sympathize. I think two design elements are being conflated here, and it would be worthwhile splitting them out. For correctness, you need to make sure any routines called from an ISR don't clobber equivalent routines called from mainline code. For

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/virtio_pci.c index 9be59d9..ee1b54c 100644 --- a/drivers/virtio/virtio_pci.c +++

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/virtio_pci.c index 9be59d9..ee1b54c 100644 --- a/drivers/virtio/virtio_pci.c +++

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/virtio_pci.c index 9be59d9..ee1b54c 100644 --- a/drivers/virtio/virtio_pci.c +++

On 07/13/2014 10:54 AM, syslinux-bot for Gene Cumm wrote: > Commit-ID: 3741886cb700e1017d70f1753f013fa10f4d9272 > Gitweb: http://www.syslinux.org/commit/3741886cb700e1017d70f1753f013fa10f4d9272 > Author: Gene Cumm <gene.cumm at gmail.com> > AuthorDate: Sun, 13 Jul 2014 11:18:50 -0400 > Committer: Gene Cumm <gene.cumm at gmail.com> > CommitDate: Sun, 13 Jul

Jim Grosbach wrote: > Hi Ali, > > Thanks for bringing this up. You're definitely under very tight design > constraints from the hardware. I can certainly sympathize. Jim, First of all, thank you very much for understanding every detail of the problem at our hand and coming up with a solution that addresses every aspect of it. IMO, given the constraints, this is probably the best

Hi, Apparently, there is no explicit support for ISRs in the llvm framework. I could not find a matching attribute that can be used to mark a function as an ISR, which codegen and optimizer can use accordingly. ISRs aren't called explicity from any function, so currently the optimizer deletes them. We are planning to introduce a new "interru...

Bringing it up again. - Sanjiv Sanjiv Gupta wrote: > Chris Lattner wrote: > >> We should discuss this on llvmdev, I think it came up before but there >> was no conclusive plan that was proposed. >> > The approach that we thought for PIC16 can be described in a > single line as below. > > "Keep the functions called from ISR and main separate by

I have a high end IBM system with 4 HT CPUs, am running xen-unstable with only Dom0 active, and I get lots of "Timer ISR/n: Time went backwards" messages. This is a short segment from dmesg: Timer ISR/1: Time went backwards: -259000 4465110000000 9741000 4465120000000 Timer ISR/6: Time went backwards: -224000 4465110000000 9776000 4465120000000 Timer ISR/6: Time went backwards: -159000

Am 04.03.20 um 11:16 schrieb Dylan McKay: > > The new are of xmega3 architecture, which is already included. So this > should be simple. > > Where is the information about ISR-vector table, SRAM addresses and so > on stored? > > > At the moment, this is not implemented in LLVM; these details are left > to the frontend. Clang/compiler-rt does not

...++ function needs to be declared with either the calling > convention avr-interrupt or avr-non-blocking-interrupt.* Skipping > this step will cause regular ret instructions to be emitted for > return-from-subroutine, instead of the required reti for interrupt > handlers. ISRs also have stricter requirements on which registers > must not be clobbered after execution, which the backend will handle > properly by restoring all clobbered registers in the interrupt > handler epilogue > * *The symbol names of the ISR function handlers must match those...

Chris Lattner wrote: > > On Aug 21, 2009, at 11:13 AM, Alireza.Moshtaghi at microchip.com wrote: > >>>> Add a pass to do call graph analyis to overlay the autos and frame >>>> sections of >>>> leaf functions. This pass will be extended to color other nodes of >>>> the call tree >>>> as well in future. >>> >>>

...these to be included in llvm-2.8 Thanks, -Ali > -----Original Message----- > From: Sanjiv Kumar Gupta - I00171 > Sent: Wednesday, August 26, 2009 11:41 AM > To: Jim Grosbach > Cc: Alireza Moshtaghi - C13012; clattner at apple.com; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] ISRs for PIC16 [was [llvm]r79631 ...] > > Jim Grosbach wrote: > > Hi Ali, > > > > Thanks for bringing this up. You're definitely under very tight design > > constraints from the hardware. I can certainly sympathize. > Jim, > First of all, thank you very much for...

...h either the calling > >     convention avr-interrupt or avr-non-blocking-interrupt.* Skipping > >     this step will cause regular ret instructions to be emitted for > >     return-from-subroutine, instead of the required reti for interrupt > >     handlers. ISRs also have stricter requirements on which registers > >     must not be clobbered after execution, which the backend will > handle > >     properly by restoring all clobbered registers in the interrupt > >     handler epilogue > >   * *The symbol names...

On Sun, Jul 13, 2014 at 10:26 PM, H. Peter Anvin <hpa at zytor.com> wrote: > On 07/13/2014 10:54 AM, syslinux-bot for Gene Cumm wrote: >> Commit-ID: 3741886cb700e1017d70f1753f013fa10f4d9272 >> Gitweb: http://www.syslinux.org/commit/3741886cb700e1017d70f1753f013fa10f4d9272 >> Author: Gene Cumm <gene.cumm at gmail.com> >> AuthorDate: Sun, 13 Jul 2014