search for: isr

...event. Is that occasional? I tend to say: no. Please see an excerpt below. And if it''s not occasional, what could I do? And by the way: I found no code that TSC will get adjusted, so I think it will get worse over the time... Thanks, Carsten. messages.0:Jan 9 12:25:15 data kernel: Timer ISR/1: Time went backwards: delta=-12018171 delta_cpu=115981829 shadow=75780489375160 off=410607630 processed=75780912000000 cpu_processed=75780784000000 messages.0:Jan 9 12:25:16 data kernel: Timer ISR/1: Time went backwards: delta=-16026092 delta_cpu=75973908 shadow=75780489375160 off=806599392 proc...

...(including locals, arguments and spills); then, to save memory, we overlay the frame of functions that are not on the same call branch. Consequently, functions are non reentrant. We can sacrifice recursion (because of other limitations in pic16 architecture) but still reentrancy is needed because ISR thread can call same function that is also called from main thread; examples are stdlib functions and intrinsic for math (div/mul/float/etc) Here is what we did - but was rejected and we would like to know which part (if any) we can keep and which part we must change: 1- Root ISR function is define...

MSIX spec requires that device can be operated with all vectors masked, by polling. So the following patchset (lightly tested) adds this ability: when driver reads ISR, the device recalls a pending notification, and returns pending status in the ISR register. The polling driver can operate as follows: - map all VQs and config to the same vector - poll ISR to get status - this also flushes VQ updates to memory - handle config change or VQ event depending on ISR...

MSIX spec requires that device can be operated with all vectors masked, by polling. So the following patchset (lightly tested) adds this ability: when driver reads ISR, the device recalls a pending notification, and returns pending status in the ISR register. The polling driver can operate as follows: - map all VQs and config to the same vector - poll ISR to get status - this also flushes VQ updates to memory - handle config change or VQ event depending on ISR...

The behaviour of default ISRs as provided by the BIOS varies wildly between platforms. Some will simply iret, some will send EOI, some will send EOI and disable the interrupt at the PIC, some will crash the machine due to single-bit errors in the ISR address. When PXENV_UNDI_ISR_IN_START returns PXENV_UNDI_ISR_OUT_NOT_OURS,...

...r bringing this up. You're definitely under very tight design constraints from the hardware. I can certainly sympathize. I think two design elements are being conflated here, and it would be worthwhile splitting them out. For correctness, you need to make sure any routines called from an ISR don't clobber equivalent routines called from mainline code. For efficiency, you want to overlay the static stack frames of functions as much as possible when you can prove those frames do not interfere. I believe you can solve these problems orthogonally with a bit of fiddling. Parall...

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/v...

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/v...

Use isr field instead of direct access to ioaddr. This way generalizes easily to virtio 1.0. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- drivers/virtio/virtio_pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/v...

...ttp://www.syslinux.org/commit/3741886cb700e1017d70f1753f013fa10f4d9272 > Author: Gene Cumm <gene.cumm at gmail.com> > AuthorDate: Sun, 13 Jul 2014 11:18:50 -0400 > Committer: Gene Cumm <gene.cumm at gmail.com> > CommitDate: Sun, 13 Jul 2014 11:18:50 -0400 > > PXE ISR: Force polling on select hardware WORKAROUND > > Like 2fe3a7bd, certain Dell machines (OptiPlex 990) state interrupts > should work but effectively don't. Force polling. > > Reported-by: Alexander Perlis <aperlis at math.lsu.edu> > Signed-off-by: Gene Cumm <gene.cu...

...n that addresses every aspect of it. IMO, given the constraints, this is probably the best design we can implement. In this email, my queries/observations mostly relate to the implementation details. > To straightforwardly create parallel call trees, one for the mainline > and one for the ISR, I believe it will be best to create two versions > of every function that's compiled very early in the process, before > any lowering of frames to static addresses or anything of that sort is > done.The ISR-tree functions should be flagged as such and have their > names mangled...

Hi, Apparently, there is no explicit support for ISRs in the llvm framework. I could not find a matching attribute that can be used to mark a function as an ISR, which codegen and optimizer can use accordingly. ISRs aren't called explicity from any function, so currently the optimizer deletes them. We are planning to introduce a new "interr...

...ote: > >> We should discuss this on llvmdev, I think it came up before but there >> was no conclusive plan that was proposed. >> > The approach that we thought for PIC16 can be described in a > single line as below. > > "Keep the functions called from ISR and main separate by cloning the > shared ones". > > >> In short, I think that this sort of thing should be modeled as an >> attribute on function definitions, not declarations. I don't >> understand why you need to clone entire call graphs, but this is b...

I have a high end IBM system with 4 HT CPUs, am running xen-unstable with only Dom0 active, and I get lots of "Timer ISR/n: Time went backwards" messages. This is a short segment from dmesg: Timer ISR/1: Time went backwards: -259000 4465110000000 9741000 4465120000000 Timer ISR/6: Time went backwards: -224000 4465110000000 9776000 4465120000000 Timer ISR/6: Time went backwards: -159000 4465110000000 9841000 44...

Am 04.03.20 um 11:16 schrieb Dylan McKay: > > The new are of xmega3 architecture, which is already included. So this > should be simple. > > Where is the information about ISR-vector table, SRAM addresses and so > on stored? > > > At the moment, this is not implemented in LLVM; these details are left > to the frontend. Clang/compiler-rt does not include the usual ISR table > or AVR-specific startup routines to initialize SRAM from program memory &...

...++ function needs to be declared with either the calling > convention avr-interrupt or avr-non-blocking-interrupt.* Skipping > this step will cause regular ret instructions to be emitted for > return-from-subroutine, instead of the required reti for interrupt > handlers. ISRs also have stricter requirements on which registers > must not be clobbered after execution, which the backend will handle > properly by restoring all clobbered registers in the interrupt > handler epilogue > * *The symbol names of the ISR function handlers must match thos...

...ld like to know exactly why in your view. > > We should discuss this on llvmdev, I think it came up before but there > was no conclusive plan that was proposed. The approach that we thought to for for PIC16 can be described in a single line as below. "Keep the functions called from ISR and main separate by cloning the shared ones". > > In short, I think that this sort of thing should be modeled as an > attribute on function definitions, not declarations. I don't > understand why you need to clone entire call graphs, but this is best > discussed on l...

...e point expressed concerns about cloning the entire function hierarchy ... Here I'm trying to stick to implementation and solicit your feedback regarding whether we are doing them in the right place. In summary, the discussion is comprised of three topics: 1) Separating the context of main vs isr functions 2) Function frame Overlay (function coloring) 3) Handling of Intrinsics for non-native operations Implementation for (1) I see Jim's suggestion - to duplicate all functions - at the center of the solution. I think doing this in the front-end (clang) makes the problem too widespread....

..._end> 9a: 08 95 ret and in C++ mode: 00000074 <_Z11__vector_21v>: 74: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <__data_end> 78: 80 93 61 00 sts 0x0061, r24 ; 0x800061 <v2> 7c: 08 95 ret So, in C++ mode it is not recognized as ISR due to name mangling. Furthermore there are no register push/pos and no reti. Whats wrong? Thanks. Am 11.03.20 um 08:13 schrieb Dylan McKay: > Here you go Wilhelm, > > https://github.com/dylanmckay/clang-avr-libc-interrupt-example > > > > On Thu, Mar 5, 2020 at 4:05 AM...

...commit/3741886cb700e1017d70f1753f013fa10f4d9272 >> Author: Gene Cumm <gene.cumm at gmail.com> >> AuthorDate: Sun, 13 Jul 2014 11:18:50 -0400 >> Committer: Gene Cumm <gene.cumm at gmail.com> >> CommitDate: Sun, 13 Jul 2014 11:18:50 -0400 >> >> PXE ISR: Force polling on select hardware WORKAROUND >> >> Like 2fe3a7bd, certain Dell machines (OptiPlex 990) state interrupts >> should work but effectively don't. Force polling. >> >> Reported-by: Alexander Perlis <aperlis at math.lsu.edu> >> Signed-off-by:...