search for: ispseudo

> I think pseudo-instructions should also define isPseudo = 1 Ah yes, thank you. > I expect that before your custom inserter, the value produced by your pseudo instruction was in a vreg. You just have to reuse this vreg to put the result of your "stuff". > If you run llc with --print-before-all, you should be able to see the actual seq...

> it should be expanded late: In lib/Target/X86/X86MCInstLower.cpp. This is exactly what I was missing. Thanks a ton! :) -- Sanjoy Das http://playingwithpointers.com

...e splitting. 3. *MCInstLower.cpp - For instructions that need to trick all of codegen. Pseudos should be expanded as early as possible. Many of the instructions currently expanded in X86MCInstLower could be moved to the PostRA expansion pass. That would also allow them to be converted into pure isPseudo=1 instructions instead of just isCodeGenOnly=1. /jakob

...``` let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mpx_bndmk: Intrinsic<[llvm_x86bnd_ty], [llvm_ptr_ty, llvm_i64_ty], []>; } ``` And following instruction that is generated when @llvm.x86.mpx.bndmk is used in code: ``` let isPseudo = 1 in let usesCustomInserter = 1 in def BNDMK64rm_Int: PseudoI<(outs BNDR:$dst), (ins i64mem:$src, GR64:$shift), [(set BNDR:$dst, (int_x86_mpx_bndmk addr:$src, i64:$shift))]>; ``` Everything works completely fine, intrinsic gets matched. But if I add "IntrNoMem" attribute to i...

...d != lval->defs.end();) { Value *slot = mem ? static_cast<Value *>(mem) : new_LValue(func, FILE_GPR); Value *tmp = NULL; @@ -1787,13 +1786,13 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst) assert(defi); if (defi->isPseudo()) { d = lval->defs.erase(d); - --d; if (slot->reg.file == FILE_MEMORY_LOCAL) to_del.insert(defi); else defi->setDef(0, slot); } else { spill(defi, slot, dval); + d++;...

...ST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>; def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>; // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the // register class is constrained to GR8_NOREX. let isPseudo = 1 in def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask), "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>; } // Defs = [EFLAGS] def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL, &quot...

Hi all, I'm playing with intrinsics and I was wondering how to lower an intrinsic that should return, for example, an int1? More precisely, how to return the value when working with MachineInst? First, I have defined an instrinsic in "Intrinsics.td": _def int_antivm : Intrinsic<[llvm_i1_ty], [], [], "llvm.antivm">;_ Then I want to lower it in the X86 backend,

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed

...to have the spill instructions in the use list here. while (!dval->uses.empty()) { - ValueRef *u = dval->uses.front(); + ValueRef *u = *dval->uses.begin(); Instruction *usei = u->getInsn(); assert(usei); if (usei->isPseudo()) { -- 1.8.4.5

...%0* *}* *declare i32 @llvm.foo.i32.i32(i32, i32)* ******************************************************************************************* In InstroInfo.td, I define a pseudo instruction like this : ****************************************************************************************** *let isPseudo = 1 in {* * def FOO : MyPseudoInst<(outs GRRegs:$dst) , (ins GRRegs:$src1, GRRegs:$src2),* * "foo $dst, $src1, $src2",* * [(set i32:$dst, (int_foo i32:$src1, i32:$src2))]> {* * }* *} * ******************************************************...

...tput(Instruction *st) return; // check def instruction can store - Instruction *di = st->getSrc(1)->defs.front()->getInsn(); + Instruction *di =(*st->getSrc(1)->defs.begin())->getInsn(); // TODO: move exports (if beneficial) in common opt pass if (di->isPseudo() || isTextureOp(di->op) || di->defCount(0xff, true) > 1) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 5ab6570..7bb28c6 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/no...

...tput(Instruction *st) return; // check def instruction can store - Instruction *di = st->getSrc(1)->defs.front()->getInsn(); + Instruction *di =(*st->getSrc(1)->defs.begin())->getInsn(); // TODO: move exports (if beneficial) in common opt pass if (di->isPseudo() || isTextureOp(di->op) || di->defCount(0xff, true) > 1) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 9c06d04..ab28f3a 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0...

...gt; 3. *MCInstLower.cpp - For instructions that need to trick all of codegen. > > Pseudos should be expanded as early as possible. Many of the instructions currently expanded in X86MCInstLower could be moved to the PostRA expansion pass. That would also allow them to be converted into pure isPseudo=1 instructions instead of just isCodeGenOnly=1. FWIW, even those expanded at MCLowering time can be pure pseudos. There is no need to use isCodeGenOnly definitions for any new code. Those that exist are pure legacy. -Jim

Hi, I have a basic machine function pass in this fashion: bool Foo::runOnMachineFunction(MachineFunction &Fn) { for (auto &BB : Fn) { for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) { if (I->isPseudo()) continue; // inspect opcode of I here } } } return true; } As the comment suggests I want to inspect the target-specific opcode of each instruction. By opcode I mean the actual machine code (=encoding of that in struction as an array of bytes), not the integer descri...

https://bugs.freedesktop.org/show_bug.cgi?id=79462 Priority: medium Bug ID: 79462 Assignee: nouveau at lists.freedesktop.org Summary: [NVC0/Codegen] Shader compilation falis in spill logic Severity: normal Classification: Unclassified OS: All Reporter: imirkin at alum.mit.edu Hardware: Other

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

...get this implies that RC->getSize will no longer be > available in the MC layer. Another advantage of this work that hasn't been mentioned yet is it will reduce the number of uses of isCodeGenOnly. The comment in Target.td indicates the long-term plan is to remove the distinction between isPseudo and isCodeGenOnly. A closely related to variable-sized register classes is the case where you have multiple registers with the same AsmName. This crops up in the same kind of cases where you have multiple instructions with the same encoding. Without a workaround, an assert is tripped in llvm-tblge...

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set

...+} > +def CONST : Constants; > + > +def FP_ZERO : PatLeaf < > + (fpimm), > + [{return N->getValueAPF().isZero();}] > +>; > + > +def FP_ONE : PatLeaf < > + (fpimm), > + [{return N->isExactlyValue(1.0);}] > +>; > + > +let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in { > + > +class CLAMP <RegisterClass rc> : AMDGPUShaderInst < > + (outs rc:$dst), > + (ins rc:$src0), > + "CLAMP $dst, $src0", > + [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] > +>; > + >...

OK, so there's a bunch of stuff in here. The geometry stuff is based on the work started by Bryan Cain and Christoph Bumiller. Patches 01-12: Add support for geometry shaders and fix related issues Patches 13-14: Make it possible for fb clears to operate on texture attachments with an explicit layer set (as is allowed in gl 3.2). Patches 15-17: Make ARB_texture_multisample work