search for: ispc

An addition for the publications page on llvm.org (and of potential interest to other people using LLVM for high-performance SIMD computation.) The ispc project would never have been possible without LLVM; many thanks to all involved in the LLVM project for building such a great system. Thanks, -matt ispc: A SPMD Compiler for High-Performance CPU Programming Matt Pharr and William R. Mark Innovative Parallel Computing (InPar) 2012 http://cloud.g...

Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We rely on LLVM's ability to produce effi...

Today Intel launched ispc, the Intel SPMD Program Compiler, an open-source compiler built on top of LLVM. It is available in both source and binary form from http://ispc.github.com/, under a BSD license. The goal of ispc is to provide a high-performance implementation of a C-based SPMD language for CPUs. The SPMD model h...

Hi Nadav, ISPC is generating long vectors (on corresponding ISPC targets) this way since the every beginning of ISPC as far as I know. There's no such things in official LLVM documents as "illegal vectors", so people do expect that arbitrary long vectors are supported and generated reasonably well....

Hi Dmitry, ISPC does some instruction selection as part of vectorization (on ASTs!) by placing intrinsics for specific operations. The SEXT to i32 pattern was implemented because LLVM did not support vector-selects when this code was written. Can you submit a small SSE4 test case that demonstrates the problem...

...s is a known problem with legalizing vector masks. The type <8 x i1> is legalized to 8 x i16, on SSE, but your operands are legalized to <4 x i32>. Type-legalization is performed per-node and we don’t have a good way to support instructions that mix the mask and operand type. Why does ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to split the vectors to increase ILP ? In that case ISPC should generate two vectors operations. Thanks, Nadav On Oct 25, 2013, at 2:16 PM, Dmitry Babokin <babokin at gmail.com> wrote: > Nadav, > > The problem...

Nadav, Could you please have a look at bug #16941 and let us know what you think about it? It's performance regression after one of your commits. Thanks. Dmitry. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131021/036e81d6/attachment.html>

Hi Dmitry. This looks like an ISPC workload. ISPC works around a limitation in selection dag which does not know how to legalize mask types when both 128 and 256 bit registers are available. ISPC works around this problem by expanding the mask to i32s and using intrinsics. Can you please verify that this regression only happens on A...

...izer should care the most about the latest silicon. > > > I am interested in looking at the SSE4 code because lowering of AVX code > is more complicated, especially for masks. The problem that <8 x i1> can > be legalized to <8 x i32> for YMM, or <8 x i16> for XMM. ISPC worked > around this limitation by explicitly extending the mask. The SEXT > canonicalization reverted the code pattern that ISPC generated. > > Thanks, > Nadav > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/ll...

Nadav, You are right, ISPC may issue intrinsics as a result of AST selection. Though I believe that we should stick to LLVM IR whenever is possible. Intrinsics may appear to be boundaries for optimizations (on both data and control flow) and are generally not optimizable. LLVM may improve over time from performance stand poi...

Kostya, all, I'm trying to build my project by clang 3.8rc1 with enabled asan (clang itself is address sanitized) and it fails on several files from my project (ISPC, https://github.com/ispc/ispc). I've reproduced this on MacOS and Linux. Please let me know if you need any other info. How to reproduce: 1) Build address sanitized clang 3.8rc1: cd /path-to-working-dir svn co http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_380/rc1/ llvm cd llvm/tools svn...

...t;,    LLVM Developers Mailing     List <llvmdev at cs.uiuc.edu> Subject: Re: [LLVMdev] Bug #16941 Message-ID:     <CACRFwuiGHNo_QdX_Ty+gij4PzHhMyyzpvm-2Lco0gdqNXSw8LQ at mail.gmail.com> Content-Type: text/plain; charset="iso-8859-1" Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We rely on LLVM's ability to produce effi...

On my Centos 7 update, into "journalctl -f" I have tons of this kind of message > feb 17 23:52:09 s-ispc.local systemd-logind[663]: Got message type=signal sender=:1.0 destination=n/a object=/org/freedesktop/systemd1/unit/php_2dfpm_2eservice interface=org.freedesktop.DBus.Properties member=PropertiesChanged cookie=17152 reply_cookie=0 error=n/a > feb 17 23:52:09 s-ispc.local systemd-logind[663]: Go...

The FreeBSD port for the Intel's ISPC compiler fails to build because it can't find this symbol: |llvmutil.cpp:(.text+0x3d60): undefined reference to `llvm::Value::dump() const' How to build LLVM to preserve these symbols? I suspect there is a cmake switch for this? Thank you, Yuri | -------------- next part --------------...

...Seems that vectorizer should care the most about the latest silicon. > I am interested in looking at the SSE4 code because lowering of AVX code is more complicated, especially for masks. The problem that <8 x i1> can be legalized to <8 x i32> for YMM, or <8 x i16> for XMM. ISPC worked around this limitation by explicitly extending the mask. The SEXT canonicalization reverted the code pattern that ISPC generated. Thanks, Nadav -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/201310...

Thanks for the reply, they were very helpful. Is it enough to prevent BBVectorize from packing together double precision instructions? If a non-clang frontend is used, such as ISPC, is it possible that the IR may contain packed double instruction? Tyler From: Cameron McInally [mailto:cameron.mcinally at nyu.edu] Sent: Thursday, February 21, 2013 6:39 PM To: Nowicki, Tyler Cc: Nadav Rotem; LLVM Developers Mailing List Subject: Re: [LLVMdev] Generate scalar SSE instructions in...

On Thu, Feb 21, 2013 at 12:14 PM, Nadav Rotem <nrotem at apple.com> wrote: > You can change the input LLVM-IR. > > On Feb 21, 2013, at 7:16 AM, "Nowicki, Tyler" <tyler.nowicki at intel.com> > wrote: > > Hi,**** > > ** ** > > I am interested in evaluating the performance of packed vs scalar > double-precision floating point instructions on

Hi, We are starting to work on an LLVM loop vectorizer. There's number of different projects that already vectorize LLVM IR. For example Hal's BB-Vectorizer, Intel's OpenCL Vectorizer, Polly, ISPC, AnySL, just to name a few. I think that it would be great if we could collaborate on the areas that are shared between the different projects. I think that refactoring LLVM in away that would expose target information to IR-level transformations would be a good way to start. Vectorizers, as well a...

...r/gather instructions (available in AVX2, for example). I believe that this feature was requested on the mailing list before. As mentioned by Hal Finkel earlier today, this feature is desired by autovectorizers as it simplifies the abstraction. I can also mention the Intel OpenCL Autovectorizer and ISPC as two other vectorizers which would benefit from this type. 2. The type Vectors-of-pointers is similar to the pointer type, in the sense that it cannot be bit-casted and it has no size. It supports the following conversions: a. Bitcast to other vector-of-pointers, as long as the element count i...

...addps %xmm2, %xmm0 .LBB0_3: # %none_on leaq 904(%rsp), %rsp ret The critical anti-dependency breaking code changes XMM0 to XMM9, preventing the proper value from being returned in XMM0. The program that generates this code is the Intel SPMD Program Compiler (ispc.github.net), which uses LLVM for back end code generation and optimization. It seems obvious that the anti-dependency breaking code is not aware that the value in XMM0 is implicitly consumed by the RET instruction. Could one of you tell me where in the LLVM source code I should be looking to fin...