search for: islabel

On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > Tom, > > What is in your isSchedulingBoundary? If it contains isLabel you might > need to disable that assert: > > assert(!MI->isTerminator() && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > > Sergei Larin > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Fo...

Tom, What is in your isSchedulingBoundary? If it contains isLabel you might need to disable that assert: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); Sergei Larin -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. > -----Original Message----- > F...

Hi, I'm trying to use the VLIWPacketizerList to schedule instructions for the R600 target, and I'm running into this assertion failure: ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels! I think I might not be using the VLIWPacketizerList class correctly. I've attached my code to this email. Can anyone spot what I'm doing wrong? Also, I had to add a LiveIntervals

...Larin > Cc: 'Anshuman Dasgupta'; llvmdev at cs.uiuc.edu > Subject: Re: VLIWPacketizerList: failing to schedule terminators > > On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > > Tom, > > > > What is in your isSchedulingBoundary? If it contains isLabel you > might > > need to disable that assert: > > > > assert(!MI->isTerminator() && !MI->isLabel() && > > "Cannot schedule terminators or labels!"); > > > > Sergei Larin > > > > -- > > Qualcomm Innova...

...on/bundling. As such we need to handle pretty much all instructions and any terminators, including labels (though I know it sounds strange). Nevertheless, ScheduleDAGInstrs::buildSchedGraph still has this hard assert in it: assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() && "Cannot schedule terminators or labels!"); ...and we have been OK till now by simply disabling it in our local version of the code, but since we are now working towards upstreaming all our code, this could no longer be ignored. I guess my proposal is not to tre...

...eed to handle > pretty much all instructions and any terminators, including labels (though I > know it sounds strange). Nevertheless, ScheduleDAGInstrs::buildSchedGraph > still has this hard assert in it: > > assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > > ...and we have been OK till now by simply disabling it in our local version > of the code, but since we are now working towards upstreaming all our code, > this could no longer be ignored. > >...

On Feb 8, 2013, at 12:28 PM, Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> wrote: > On 02/08/2013 08:20 PM, Tobias Grosser wrote: >> That sounds elegant and seems to solve the correctness problems. > > There is no big difference here except that the memory instructions > would not need the metadata. > > I do not think the abundance of metadata is really the

...p =================================================================== --- lib/Target/ARM/ARMInstrInfo.cpp (revision 14) +++ lib/Target/ARM/ARMInstrInfo.cpp (working copy) @@ -904,7 +904,8 @@ return TAI->getInlineAsmLength(MI- >getOperand(0).getSymbolName()); if (MI->isLabel()) return 0; - if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) + if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF || + MI->getOpcode() == TargetInstrInfo::DECLARE) return 0; Same for ARM::DBG_LABEL. 3. + case ISD::DECLARE: { + SDValue C...

...asgupta'; llvmdev at cs.uiuc.edu > > Subject: Re: VLIWPacketizerList: failing to schedule terminators > > > > On Thu, Mar 29, 2012 at 01:50:58PM -0500, Sergei Larin wrote: > > > Tom, > > > > > > What is in your isSchedulingBoundary? If it contains isLabel you > > might > > > need to disable that assert: > > > > > > assert(!MI->isTerminator() && !MI->isLabel() && > > > "Cannot schedule terminators or labels!"); > > > > > > Sergei Larin > > &gt...

Hi all, FlexyCore, the company I am working for, use LLVM to generate binary for ARM platform. We are very fulfilled with LLVM, and FlexyCore will be pleased to contribute on this software. We need debug support in ARM binary, but, in LLVM 2.4, this support is not activated for ARM backend. Consequently, I made small modifications in order to activate it (see the patch in attach file). My