search for: iskill

Hello llvmers: I'm study Fast register allocation in codegen. I get confused with isKill flag in MachineOperand. I thin "isKill" flag the last Use Reference. But, Fast Register doesn't require LiveVariable Analysis which will mark isKill Flag for global virtual Register. So during Fast RegisterAllocation, Faster Register Allocation procedure can't determine if...

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same thing. > R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1-&...

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Use...

Is there anything that documents what these properties (and the other similar properties) do on the MachineOperand class? I’m trying to debug an instruction selection issue I think. It’s hard to find documentation on what the MO properties mean. Thanks, Carl

...tructions”? > On 11 Mar 2019, at 16:43, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi Carl, > > Look at the comments in include/llvm/CodeGen/MachineOperand.h for the documentation of the various flags. > > IsDead means that a definition is never used. > IsKill means that this is the last use of a given register. > > Cheers, > -Quentin > >> On Mar 11, 2019, at 8:54 AM, LLVM Mailing List via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Is there anything that documents what these properties (and the other similar...

Hello llvmers: I'm study Fast register allocation in codegen. I get confused with isKill flag in MachineOperand. I thin "isKill Because Fast Register doesn't require LiveVariable Analysis , So during Fast RegisterAllocation, the Allocation procedure can't determine if this use reference is the last use ( isKill flag is missed for global Virtual register without pre-pas...

...it register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(1) .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); After this store I catch assertion failed: "Instruction not found in maps", because only last of this instruction added in Instruction maps. How can I avoid assertion failed in this case? Best regards, Dmitriy.

...========================================== --- AggressiveAntiDepBreaker.cpp (revision 186828) +++ AggressiveAntiDepBreaker.cpp (working copy) @@ -399,7 +399,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; // Ignore KILLs and passthru registers for liveness... - if (MI->isKill() || (PassthruRegs.count(Reg) != 0)) + if (MI->isKill() || (PassthruRegs.count(Reg) != 0) || TII->isPredicated(MI)) continue; // Update def for Reg and aliases.

...ons after register allocation is not safe because there is no way to know which register definitions were physical registers before RA (e.g. to meet ABI or ISA constraints) and thus should not be changed. I'd like to propose adding a bit to MachineOperand (by overloading the meaning of the IsKill bit for defs, so no extra storage would be required), that tracks whether a given register definition was a virtual register before RA. I'll throw out 'IsRenameable' for a potential name. Register definitions created with virtual registers would have this bit set. This bit should...

...f8d23da5e76b598b8327ef239bc/lib/Target/Picoblaze /******************************/ void PicoblazeInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI ) const { PR_FUNCTION(); DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &M...

...two > instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "Instruction not found in > maps", because only last of this instruction added in Instruction maps. > How can I avoid assertion failed in this case? > > Best regards, Dmitriy. > > ___________________...

...These return an unsigned int "register number"; but I'm not sure how to identify which register actually corresponds to that number. Also, I will need to identify definitions and uses of registers in instructions. I see that MachineOperand has methods such as isUse(), isDef(), and isKill(), which sound like they might be relevant to what I'm doing; but neither the Doxygen nor the source are particularly helpful as to what they actually do. From the MachineInstr documentation, I gathered that instructions which define a value are always written so that the value being defined is...

...MachineOperand &Reg = OldMI->getOperand(0); MachineOperand &Imm = OldMI->getOperand(1); assert(Reg.isReg()); assert(Imm.isImm()); imm = Imm.getImm(); if (imm >= 32) continue; kill = getKillRegState(Reg.isKill()); switch (Reg.getReg()) { default: assert(false); case X86::RAX: case X86::EAX: case X86::AX: if (imm < 8) NewMI = BUILD_INS(TEST8i8, AL, 1 << imm); else if (imm < 16) NewMI = BUILD_INS(TES...

...- The IsDef flag is implied by the use of the register before the '=', unless it's implicit. - TiedTo and IsEarlyClobber aren't not serialized, as they are defined by the instruction description. (I believe that's true in all cases, but I'm not 100% sure). - IsUndef, IsImp, IsKill, IsDead, IsInternalRead, IsDebug - keywords like 'implicit', 'undef', 'kill', 'dead' are used before the register e.g. 'undef %rax', 'implicit-def kill %eflags'. I don't have a syntax for the SubReg_TargetFlags at the moment. Alex > >...

...flags will be valid after this pass completes. (2) At the top of LiveVariables.h, "If a physical register is not register allocatable, it is not tracked. This is useful for things like the stack pointer and condition codes." This suggests that the pass cannot restore the MachineOperand::IsKill and MachineOperand::IsDead bits for physical non-register-allocatable registers. I would appreciate any feedback. If we decide this is buggy, I'll work on a fix. I have tested this on 3.6.1. I have not yet tested on the 3.7 series as it may take some effort to port my out-of-tree target....

...er > allocation is not safe because there is no way to know which register > definitions were physical registers before RA (e.g. to meet ABI or ISA > constraints) and thus should not be changed. I'd like to propose adding a > bit to MachineOperand (by overloading the meaning of the IsKill bit for > defs, so no extra storage would be required), that tracks whether a given > register definition was a virtual register before RA. I'll throw out > 'IsRenameable' for a potential name. > > > > Register definitions created with virtual registers would have...

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;

Hi Violeta, I compiled with clang -Oz and clang -Oz -mno-red-zone for comparisons against Oz and clang -O0 and clang -O0 -mno-red-zone for comparisons against a default clang. I unfortunately don’t have the clang commit I worked with on my home laptop, and don’t have access to the computer I was using at Apple, so I can’t help you there. Jessica > On Sep 28, 2016, at 11:22 AM, Violeta

...ber, only valid for MO_Register. A > value of 0 > + /// indicates the MO_Register has no subReg. > + unsigned char SubReg; > + > + /// TargetFlags - This is a set of target-specific operand flags. > + unsigned char TargetFlags; > + }; > > /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for > MO_Register > /// operands. > @@ -176,9 +179,17 @@ > /// > MachineOperandType getType() const { return > (MachineOperandType)OpKind; } > > - unsigned char getTargetFlags() const { return TargetFlags; } > - void setTarg...

...e register before the '=', >> unless it's implicit. >> - TiedTo and IsEarlyClobber aren't not serialized, as they are defined by >> the instruction description. (I believe that's true in all cases, but I'm >> not 100% sure). >> - IsUndef, IsImp, IsKill, IsDead, IsInternalRead, IsDebug - keywords like >> 'implicit', 'undef', 'kill', 'dead' are used before the register e.g. >> 'undef %rax', 'implicit-def kill %eflags'. >> I don't have a syntax for the SubReg_TargetFlags at the mo...