Displaying 20 results from an estimated 22 matches for "isdots".
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2013 Apr 12
2
[LLVMdev] TableGen list merging
Hi,
In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register:
class isDOT {
list<Register> Defs = [CR0];
bit RC = 1;
}
and this gets used on instructions such as:
def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"addic. $rD, $rA, $imm", IntGeneral,
2013 Apr 12
0
[LLVMdev] TableGen list merging
On Apr 12, 2013, at 2:06 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register:
>
> class isDOT {
> list<Register> Defs = [CR0];
> bit RC = 1;
> }
>
> and this gets used on instructions such as:
>
> def ADDICo : DForm_2<13,
2013 Apr 12
1
[LLVMdev] TableGen list merging
----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> Sent: Friday, April 12, 2013 11:36:49 AM
> Subject: Re: [LLVMdev] TableGen list merging
>
>
> On Apr 12, 2013, at 2:06 AM, Hal Finkel
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
I'm starting to look into binary instruction encodings in TableGen, and I'm
a bit confused on how the instruction fields are populated. Perhaps I'm
just being dense, but I cannot see how SDAG operands are translated into
the encoding fields. Can someone please explain the following snippet from
the PPC back-end.
The AND instruction in PPC is defined as:
1011 def AND :
2000 Apr 03
1
2.0.7pre3: smbclient issues
My systems: rh61, 2.2.14 + smbfs-nls.patch.
I refer to 2.0.7pre3 as 2.0.7
=== 1) "ls" of an empty dir
1a)
1.9.18 doing "ls" to an empty samba dir:
smb: \> ls
49550 blocks of size 16384. 33754 blocks available
1b)
2.0.7 doing "ls" to an empty samba dir:
smb: \> ls
ERRDOS - ERRbadfile (File not found.) listing \* <=======
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com>wrote:
> On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote:
> > I'm starting to look into binary instruction encodings in TableGen, and
> I'm
> > a bit confused on how the instruction fields are populated. Perhaps I'm
> > just being dense, but I cannot see how SDAG
2012 Jul 24
0
[LLVMdev] Instruction Encodings in TableGen
On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote:
> I'm starting to look into binary instruction encodings in TableGen, and I'm
> a bit confused on how the instruction fields are populated. Perhaps I'm
> just being dense, but I cannot see how SDAG operands are translated into
> the encoding fields. Can someone please explain the following snippet from
2012 Jul 25
2
[LLVMdev] Instruction Encodings in TableGen
On Tue, Jul 24, 2012 at 8:46 PM, Jim Grosbach <grosbach at apple.com> wrote:
>
> On Jul 24, 2012, at 3:52 PM, Justin Holewinski <
> justin.holewinski at gmail.com> wrote:
>
> On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com>wrote:
>
>> On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote:
>> > I'm
2012 Jul 25
0
[LLVMdev] Instruction Encodings in TableGen
On Jul 24, 2012, at 3:52 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
> On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com> wrote:
> On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote:
> > I'm starting to look into binary instruction encodings in TableGen, and I'm
> > a bit confused on how the instruction
2012 Jul 27
0
[LLVMdev] Instruction Encodings in TableGen
On Wed, 25 Jul 2012 07:51:28 -0400
Justin Holewinski <justin.holewinski at gmail.com> wrote:
> On Tue, Jul 24, 2012 at 8:46 PM, Jim Grosbach <grosbach at apple.com>
> wrote:
>
> >
> > On Jul 24, 2012, at 3:52 PM, Justin Holewinski <
> > justin.holewinski at gmail.com> wrote:
> >
> > On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard
> >
2020 May 14
0
open 2nd pdf on dfs share with Acrobat Reader not possible
Hello everybody,
after updating samba from Version 4.9.1 to 4.10.4 (Centos 7)
opening a PDF Document in Acrobat Reader with a double click,
when the document resides on a dfs share, is only possible for the 1st
document.
I know, this is not not a samba bug, because windows 2019 Server behaves
the same, i just want to share my findings.
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Cool, that worked. New patch attached...
Cheers,
Gary
Evan Cheng wrote:
> Just cast both values to const TargetRegisterClass*.
>
> Evan
>
> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> > Evan Cheng wrote:
> > > How about?
> > >
> > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> > > &PPC:G8RCRegClass;
>
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
> prepare a updated patch?
This should work, though I won't have access to my test box now until
next Thursday so no guarantees :)
Cheers,
Gary
--
http://gbenson.net/
-------------- next part --------------
Index: lib/Target/PowerPC/PPCISelLowering.h
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36
2008 Jul 10
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Just cast both values to const TargetRegisterClass*.
Evan
On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> Evan Cheng wrote:
>> How about?
>>
>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
>> &PPC:G8RCRegClass;
>> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
>
> I tried something like that yesterday:
>
> const
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote:
> How about?
>
> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> &PPC:G8RCRegClass;
> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
I tried something like that yesterday:
const TargetRegisterClass *RC =
is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass;
but I kept getting this error no matter how I arranged it:
2008 Jun 30
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
You need to insert new basic blocks and update CFG to accomplish this.
There is a hackish way to do this right now. Add a pseudo instruction
to represent this operation and mark it usesCustomDAGSchedInserter.
This means the intrinsic is mapped to a single (pseudo) node. But it
is then expanded into instructions that can span multiple basic
blocks. See
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Ah, didn't see that, that's what comes of trying to do something at
5pm :) I attached an updated patch which creates a virtual register
instead of using R0. How does this look?
Cheers,
Gary
Dan Gohman wrote:
> PPCTargetLowering::EmitInstrWithCustomInserter has a reference
> to the current MachineFunction for other purposes. Can you use
> MachineFunction::getRegInfo instead?
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Would it be acceptable to change MachineInstr::getRegInfo from private
to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter?
Cheers,
Gary
Evan Cheng wrote:
> Look for createVirtualRegister. These are examples in
> PPCISelLowering.cpp.
>
> Evan
> On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
>
> > Hi Evan,
> >
> > Evan Cheng wrote: