search for: isbarri

...g2 %vreg3<def> = LDtocL <ga:@env_sigill>, %vreg2<kill>; mem:LD8[GOT] G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg2 %vreg4<def> = EH_SjLj_SetJmp64 %vreg3<kill>, %CTR8<imp-def,dead>; GPRC:%vreg4 G8RC:%vreg3 Currently Powerpc sets EH_SjLj_SetJmp64 with flag isBarrier. But it is also a fall-through instruction. So it fails in machineinstr verifying. I checked other platforms like X86 and ARM, they also set this intrinsics as barrier. For my understanding, a barrier instruction means control flow can not fall through like llvm.eh.sjlj.longjmp and unconditional...

isBarrier is not defined in BX_RET and tBX_RET instructions and the Machine Instructions Verifier (-verify-machineinstrs) give errors about that. Is it normal that isBarrier is not defined on these instructions ?

Hi, this is a small patch of ARM Instructions description because "-verify-machineinstrs" complains about that. This doesn't break the tests on my machine. Regards -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: patch_barrier URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090929/84aca914/attachment.ksh>

...ll instructions after the intrinsic, and this should hold after any optimization in opt and llc. Can anyone tell me if this is something available in the current LLVM infrastructure and if so, what should be the correct way to create this intrinsic/pseudo instruction? Which bit should be set to 1? isBarrier or hasSideEffects or both? I cannot find the documentation for these 2 bits other than the comments in Target.td, so I'd like to have some explanation here. Thank you so much for your help, Son Tuan Vu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http:...

...c: def int_soru_sre : Intrinsic<[llvm_void_ty, llvm_i32_ty], [IntrWriteMem]>; The lower instruction (in MIPS): class SORUI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin> { let isBarrier = 1; // or call, hassideefects, ..., nothing work } def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), "sre $imm", [(int_soru_sre imm:$imm)], IISoru>; (With IISoru I made all the possible changes: a lot of cycles or none with all the functional units or none...

...en the intrinsic is > lowered, then it doesn't matter (or perhaps the reorder is made > before). What is the description of the instruction you're lowering intrinsic into? Have you looked for the instruction flags defined in Target.td file? You instruction should definitely have "isBarrier" flag set. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University.

Hi Yang, > bnz R2, LBB0_34 > > I do not have any clue what happens when compiling with -O2. > Can someone make a suggestion? Is the "bnz" instruction marked "isBarrier" in your TableGen files? If so, that would mean LLVM considers fallthrough impossible and decides it can move LBB0_33 around at will. It's still very odd that it thinks it can put it directly before LBB0_34 though. It would be interesting to see the blocks before and after the "Bas...

Hi, guys, I compiled a subroutine with -O2, and llvm backend produced codes like: ################################################################## LBB0_32: ... R31 = -1 R20 = R31 * R20; .... bnz R2, LBB0_34 LBB0_31: ... b LBB0_34 LBB0_33: # weird basic block? R20 = R5 LBB0_34: ....

Hello, I have an intrinsic that matches to a asm instruction directly. This intrinsic starts a coprocessor that can do anything. If I put another instruction next to it (a multiplication for example), the "llc" reorders and puts the intrinsic after the multiplication. I have tried all: - Setting the instruction like if it takes 256 cycles or 0 cycles. - Setting the instruction with

I am working on a back end for an architecture whose jump via table instruction includes the range check. If the index is out of range, the jump table instruction just falls through. I implemented a pass to remove the range check generated before the jump table instruction because it is superfluous. This causes as assertion in MachineBlockPlacement.cpp:

...l and the assembly becomes invalid. I fixed this in the MBlaze backend by overriding AsmPrinter::isBlockOnlyReachableByFallthrough and replaced (at the end of the function): // Otherwise, check the last instruction. const MachineInstr &LastInst = Pred->back(); return !LastInst.getDesc().isBarrier(); with: // Check if the last terminator is an unconditional branch. MachineBasicBlock::const_iterator I = Pred->end(); while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ; // Noop return I == Pred->end() || !I->getDesc().isBarrier(); Notice, that the...

...uot;bi \$lr" works? Or "bi $$lr"? Or even something >>> like >>> !strconcat("bi ", !strconcat("$", "lr")). >> >> >> Yep, $$ should work. > > It doesn't. Here's the pattern: > > let isTerminator = 1, isBarrier = 1, noResults = 1 in { > let isReturn = 1 in { > def RET: BRForm<0b00010101100, (ops), > "bi $$lr", > BranchResolv, > [(retflag)]>; > } > } > > Output from make: > > l...

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3,

...they can be freely moved past > anything. > > The difference occasionally comes up when people want begin-benchmark > and end-benchmark intrinsics, but really the whole concept of what's > calculated between two points is pretty fuzzy. > > > Which bit should be set to 1? isBarrier or hasSideEffects or both? > > hasSideEffects is the closest, with the caveats above. > > isBarrier has nothing to do with fences. It's applied to unconditional > branches so that LLVM knows that a basic-block ending with that > instruction won't fall-through. > >...

...t;getReturnValue()==0 || + std::find(RI->op_begin(), RI->op_end(), + (Value*)&I) != RI->op_end()) + return true; + } + } + return false; +} Also, shouldn't this function be "static"? let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL", + []>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*} $dst # TAILCALL",...

...gt;> >>I am not sure. Does "bi \$lr" works? Or "bi $$lr"? Or even something >>like >>!strconcat("bi ", !strconcat("$", "lr")). > > > Yep, $$ should work. It doesn't. Here's the pattern: let isTerminator = 1, isBarrier = 1, noResults = 1 in { let isReturn = 1 in { def RET: BRForm<0b00010101100, (ops), "bi $$lr", BranchResolv, [(retflag)]>; } } Output from make: llvm[0]: Building SPU.td code emitter with tblgen tblg...

The patch is against revision 42247. -------------- next part -------------- A non-text attachment was scrubbed... Name: tailcall-src.patch Type: application/octet-stream Size: 62639 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070923/4770302f/attachment.obj>

...================================================================ > --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) > +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) > @@ -773,6 +773,10 @@ > [(store F8RC:$frS, xaddr:$dst)]>; > } > > +let isBarrier = 1 in > +def SYNC : XForm_24_sync<31, 598, (outs), (ins), > + "sync", LdStSync, > + [(int_ppc_sync)]>; > > //===----------------------------------------------------------------------===// > // PPC32 Arithmetic In...

.../Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -773,6 +773,10 @@ [(store F8RC:$frS, xaddr:$dst)]>; } +let isBarrier = 1 in +def SYNC : XForm_24<31, 598, (outs), (ins), + "sync", LdStSync, + [(int_ppc_sync)]>; //===----------------------------------------------------------------------===// // PPC32 Arithmetic Instructions. @@ -1357,5 +1361,13 @@ def : P...

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5