Displaying 6 results from an estimated 6 matches for "ir4".
Did you mean:
cr4
2007 Oct 18
1
documentation bug for isoreg example (PR#10352)
Full_Name: Benjamin Tyner
Version: 2.6.0 (43063)
OS: WinXP
Submission from: (NULL) (171.161.224.10)
At the end of the examples for isoreg, there is
cat("R^2 =", formatC(sum(residuals(ir4)^2) / (9*var(y4)), digits=2),"\n")
I think this should be
cat("R^2 =", formatC(1 - sum(residuals(ir4)^2) / (9*var(y4)), digits=2),"\n"
Thanks
Ben
platform i386-pc-mingw32
arch i386
os mingw32...
2007 Dec 14
1
segfault isoreg with NAs
Dear list,
As can be seen below, adding a NA to the y values
in a call to isoreg results in a segfault.
ir4 <- isoreg(1:10, y4 <- c(5, 9, 1:2, 5:8, NA, 8))
Adding missing values to the x values, on the contrary,
gives an error, but maybe the error message could be
tailored to this particular situation.
y <- c(5, 9, 1:2, 5:8, 3, 8)
x <- c(1:9, NA)
isoreg(x, y)
## error message: Error in if (...
2012 Aug 01
3
Neuralnet Error
I require some help in debugging this codeĀ
library(neuralnet)
ir<-read.table(file="iris_data.txt",header=TRUE,row.names=NULL)
ir1 <- data.frame(ir[1:100,2:6])
ir2 <- data.frame(ifelse(ir1$Species=="setosa",1,ifelse(ir1$Species=="versicolor",0,"")))
colnames(ir2)<-("Output")
ir3 <- data.frame(rbind(ir1[1:4],ir2))
2010 Sep 08
3
[LLVMdev] Complex regalloc contraints
...]
[ inf inf 0 inf ]
[ inf inf inf 0 ]
The rows and columns of this matrix reflect the storage locations that the
allocator can assign, and the elements represent the cost of a specific
assignment. Say the rows represent the set { or1, or2, or3, or4 } and the
columns represent { ir1, ir2, ir3, ir4 }. The infinite cost elements
constrain the valid assignments to matching pairs.
Representing the constraint is dead easy, the trick would be making the
allocator aware of the constraint. At present the PBQP allocator only
"knows" about the basic RA constraints (aliasing, classes, inter...
2010 Sep 07
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote:
> The machine I am targeting has some special requirements for some
> operations, say:
>
> ADD or1, ir1, r5
>
> would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
> 1). The point id that input and output regs have to go paired (this
> meaning an addition of ir1 with whatever always goes to
2010 Sep 07
2
[LLVMdev] Complex regalloc contraints
Hi all,
The machine I am targeting has some special requirements for some
operations, say:
ADD or1, ir1, r5
would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
1). The point id that input and output regs have to go paired (this
meaning an addition of ir1 with whatever always goes to or1, or an in
general irX + whatever goes to orX).
AFAIK, InstrInfo.td only allow