search for: invd

> On Feb 11, 2020, at 5:53 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?From: Tom Lendacky <thomas.lendacky at amd.com> > > Implement a handler for #VC exceptions caused by INVD instructions. Uh, what? Surely the #VC code can have a catch-all OOPS path for things like this. Linux should never ever do INVD.

From: Tom Lendacky <thomas.lendacky at amd.com> Implement a handler for #VC exceptions caused by INVD instructions. Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> [ jroedel at suse.de: Adapt to #VC handling infrastructure ] Co-developed-by: Joerg Roedel <jroedel at suse.de> Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/kernel/sev-es.c | 8 ++++++++ 1 fi...

Hi. I have a very quick question. Is the instruction cache flushed by the llvm jit before code in memory is written to or executed? I'm assuming so, but I can't find where in the source code this is happening. In particular I searched for clflush, invd, and wbinvd instructions, but couldn't find them. And if it's not necessary to do this, can you please explain why? (I'm assuming the target platform has a separate L1 i-cache). Thanks. - Shasank _________________________________________________________________ Hotmai...

...mail.com> wrote: > Hi.  I have a very quick question.  Is the instruction cache flushed by the > llvm jit before code in memory is written to or executed?  I'm assuming so, > but I can't find where in the source code this is happening.  In particular > I searched for clflush, invd, and wbinvd instructions, but couldn't find > them.  And if it's not necessary to do this, can you please explain why? > (I'm assuming the target platform has a separate L1 i-cache).  Thanks. On x86 in particular, explicitly flushing the instruction cache isn't necessary; the...

...ound some interesting projects but still have some questions about them: "Add support for 16-bit x86 assembly and real mode to the assembler and disassembler, for use by BIOS code. This includes both 16-bit instruction encodings as well as privileged instructions (lgdt, lldt, ltr, lmsw, clts, invd, invlpg, wbinvd, hlt, rdmsr, wrmsr, rdpmc, rdtsc) and the control and debug registers." Correct me if I'm mistaken, but isn't this already implemented in llvm mc? I haven't searched for every instruction part of these architectures but I was able find to some of the privileged ins...

...EF(GetIDT) \ + VDEF(GetTR) \ + VDEF(WriteGDTEntry) \ + VDEF(WriteLDTEntry) \ + VDEF(WriteIDTEntry) \ + VDEF(UpdateKernelStack) \ + VDEF(SetCR0) \ + VDEF(SetCR2) \ + VDEF(SetCR3) \ + VDEF(SetCR4) \ + VDEF(GetCR0) \ + VDEF(GetCR2) \ + VDEF(GetCR3) \ + VDEF(GetCR4) \ + VDEF(INVD) \ + VDEF(WBINVD) \ + VDEF(SetDR) \ + VDEF(GetDR) \ + VDEF(RDPMC) \ + VDEF(RDTSC) \ + VDEF(CLTS) \ + VDEF(EnableInterrupts) \ + VDEF(DisableInterrupts) \ + VDEF(GetInterruptMask) \ + VDEF(SetInterruptMask) \ + VDEF(IRET) \ + VDEF(SYSEXIT) \ + VDEF(Pause) \ + VDEF(Halt) \...

...EF(GetIDT) \ + VDEF(GetTR) \ + VDEF(WriteGDTEntry) \ + VDEF(WriteLDTEntry) \ + VDEF(WriteIDTEntry) \ + VDEF(UpdateKernelStack) \ + VDEF(SetCR0) \ + VDEF(SetCR2) \ + VDEF(SetCR3) \ + VDEF(SetCR4) \ + VDEF(GetCR0) \ + VDEF(GetCR2) \ + VDEF(GetCR3) \ + VDEF(GetCR4) \ + VDEF(INVD) \ + VDEF(WBINVD) \ + VDEF(SetDR) \ + VDEF(GetDR) \ + VDEF(RDPMC) \ + VDEF(RDTSC) \ + VDEF(CLTS) \ + VDEF(EnableInterrupts) \ + VDEF(DisableInterrupts) \ + VDEF(GetInterruptMask) \ + VDEF(SetInterruptMask) \ + VDEF(IRET) \ + VDEF(SYSEXIT) \ + VDEF(Pause) \ + VDEF(Halt) \...

...ifdef CONFIG_X86_ESPFIX32 - ALTERNATIVE "jmp .Lrestore_nocheck", "", X86_BUG_ESPFIX + ALTERNATIVE(jmp .Lrestore_nocheck, , X86_BUG_ESPFIX) movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS /* @@ -692,9 +692,9 @@ ENTRY(simd_coprocessor_error) pushl $0 #ifdef CONFIG_X86_INVD_BUG /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ - ALTERNATIVE "pushl $do_general_protection", \ - "pushl $do_simd_coprocessor_error", \ - X86_FEATURE_XMM + ALTERNATIVE(pushl $do_general_protection, + pushl $do_simd_coprocessor_error,...

...tions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Add handler for MMIO events x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/realm...

...tions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Add handler for MMIO events x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/realm...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...d apply_paravirt() completely. (I think Xen can be changed to set CPU feature bits to specify which ops it needs during early boot, then those ops can be patched in using early alternatives.) For more details, see the commit log in patch 11/13. Josh Poimboeuf (13): x86/paravirt: remove wbinvd() paravirt interface x86/paravirt: Fix output constraint macro names x86/paravirt: Convert native patch assembly code strings to macros x86/paravirt: Convert DEF_NATIVE macro to GCC extended asm syntax x86/paravirt: Move paravirt asm macros to paravirt-asm.h x86/paravirt: Clean up paravir...

...d apply_paravirt() completely. (I think Xen can be changed to set CPU feature bits to specify which ops it needs during early boot, then those ops can be patched in using early alternatives.) For more details, see the commit log in patch 11/13. Josh Poimboeuf (13): x86/paravirt: remove wbinvd() paravirt interface x86/paravirt: Fix output constraint macro names x86/paravirt: Convert native patch assembly code strings to macros x86/paravirt: Convert DEF_NATIVE macro to GCC extended asm syntax x86/paravirt: Move paravirt asm macros to paravirt-asm.h x86/paravirt: Clean up paravir...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...

...OIO exceptions x86/sev-es: Add CPUID handling to #VC handler x86/sev-es: Setup per-cpu GHCBs for the runtime handler x86/sev-es: Add Runtime #VC Exception Handler x86/sev-es: Handle MMIO events x86/sev-es: Handle MSR events x86/sev-es: Handle DR7 read/write events x86/sev-es: Handle WBINVD Events x86/sev-es: Handle RDTSC(P) Events x86/sev-es: Handle RDPMC Events x86/sev-es: Handle INVD Events x86/sev-es: Handle MONITOR/MONITORX Events x86/sev-es: Handle MWAIT/MWAITX Events x86/sev-es: Handle VMMCALL Events x86/kvm: Add KVM specific VMMCALL handling under SEV-ES x86/re...