Displaying 3 results from an estimated 3 matches for "intpairregclassid".
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intpairregclass
2015 Apr 02
2
[LLVMdev] How to enable use of 64bit load/store for 32bit architecture
...make i64 not be legal. Then, assuming the regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE:
SDValue ValueToBeStored = St.getOperand(…)
auto SeqOps[] = {
DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32),
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)),
DAG.getTargetConstant(SP ::sub0, MVT::i32),
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)),
DAG.getTargetConstant(SP ::sub1, MVT::i32)...
2015 Apr 03
2
[LLVMdev] How to enable use of 64bit load/store for 32bit architecture
...regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE:
>>
>> SDValue ValueToBeStored = St.getOperand(…)
>>
>> auto SeqOps[] = {
>> DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32),
>> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)),
>> DAG.getTargetConstant(SP ::sub0, MVT::i32),
>> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)),
>> DAG.getTarg...
2015 Apr 02
2
[LLVMdev] How to enable use of 64bit load/store for 32bit architecture
In http://reviews.llvm.org/D8713, I added the 64bit integer store ("std")
and load ("ldd") instructions for 32bit sparc. But now I need codegen to
know how to emit them, and am not sure the best way to go about teaching
the backend that 64bit integers can be used natively, but only for loads
and stores.
(I originally wrote an earlier draft of question in the review but it