search for: intpairregclass

...e ll code %0 = load i64, i64* @x, align 8 store i64 %0, i64* @y, align 8 turned into just "ldd, std" instructions, as it does in GCC, rather than loading and storing the two 32bit halves of the variables separately. To allow that, I tried adding: addRegisterClass(MVT::i64, &SP::IntPairRegClass) to SparcTargetLowering::SparcTargetLowering in 32bit mode. Doing that then makes load/store work. But it causes llvm to try to use i64 operations for *everything*, which of course fails for all other operations, since there's no such instruction pattern for them. Okay, so I then try setting...

...make i64 not be legal. Then, assuming the regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE: SDValue ValueToBeStored = St.getOperand(…) auto SeqOps[] = { DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32), DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)), DAG.getTargetConstant(SP ::sub0, MVT::i32), DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)), DAG.getTargetConstant(SP ::sub1, MVT::i32...

...regclass you gave has some subregs, you can give load/store a custom legalisation where you change the i64 to MVT::Untyped. So something like this for ISD::STORE: >> >> SDValue ValueToBeStored = St.getOperand(…) >> >> auto SeqOps[] = { >> DAG.getTargetConstant(SP::IntPairRegClassID, MVT::i32), >> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(0, MVT::i32)), >> DAG.getTargetConstant(SP ::sub0, MVT::i32), >> DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, ValueToBeStored, DAG.getConstant(1, MVT::i32)), >> DAG.getTa...