Displaying 5 results from an estimated 5 matches for "int_ppc_mtctr".
2014 Feb 26
2
[LLVMdev] How to 'define and use' a LOOP intrinsic that takes "iteration count" and the "label" to jump to ?
I have defined the intrinsic as
* def int_loop: Intrinsic<[],[llvm_i8_ty, llvm_empty_ty],[]>;*
and also got the Codegen backend support in Instructioninfo.td file.
Then created a .ll file to test it.
The .ll file is like this
*declare void @llvm.loop(i8, label)define void @fn() nounwind readnone
{entry: ..... ..... call void @llvm.loop(i8 10, label %entry) ret
void}*
But
2016 Jun 13
2
LLVM IR intrinsics placeholder for strings [was Re: Back end with special loop instructions (using LLVM IR intrinsics)]
...C/PPCCTRLoops.cpp) makes use of
> LLVM IR intrinsics, in this case defined at
> [LLVM_repo]/llvm/include/llvm/IR/IntrinsicsPowerPC.td, such as:
> // Intrinsics used to generate ctr-based loops. These should only be
> // generated by the PowerPC backend!
> def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>;
> def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>;
>
> And these intrinsics are instantiated in the LLVM program, for example with the
> following code in PPCCTRLoops.cpp:
> IRBuilder<&g...
2016 May 30
1
Back end with special loop instructions
Hi Alex,
You might find it useful to look at how lib/Target/PowerPC/PPCCTRLoops.cpp works.
-Hal
----- Original Message -----
> From: "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org>
> To: "llvm-dev" <llvm-dev at lists.llvm.org>
> Sent: Monday, May 30, 2016 5:09:37 PM
> Subject: [llvm-dev] Back end with special loop instructions
>
> Hello.
2016 May 30
2
Back end with special loop instructions
Hello.
I'm writing a back end for my research SIMD processor that has an assembly language
that is blocked structured, with one-level loops. An example program with my assembly
language:
REPEAT_X_TIMES(Param2)
R0 = LS[offset_A];
END_REPEAT;
The LLVM code somewhat equivalent to the above ASM program is:
vector.body:
%index = phi i64 [
2019 May 20
3
[RFC] Intrinsics for Hardware Loops
Hi,
Arm have recently announced the v8.1-M architecture specification for
our next generation microcontrollers. The architecture includes
vector extensions (MVE) and support for low-overhead branches (LoB),
which can be thought of a style of hardware loop. Hardware loops
aren't new to LLVM, other backends (at least Hexagon and PPC that I
know of) also include support. These implementations