search for: int3

I am having problems installing a custom int3 handler from a com32 app. Here is what I have tried: void int3_handler() { put_str("int3!!!"); __asm__("iret"); } void init_handlers() { struct { unsigned long limit : 16; unsigned long base : 32; } __at...

Fix the mistake for debug exception(#DB), overflow exception(#OF; generated by INTO) and int 3(#BP) instruction emulation. For INTn (CD ib), it should use type 4 (software interrupt). For INT3 (CC; NOT CD ib with ib=3) and INTO (CE; NOT CD ib with ib=4), it should use type 6 (software exception). For other exceptions (#DE, #DB, #BR, #UD, #NM, #TS, #NP, #SS, #GP, #PF, #MF, #AC, #MC, and #XM), it should use type 3 (hardware exception). In the unlikely event that you are emulating the un...

...setting breakpoints around hypercalls in a domU causes dom0 to lockup To: xen-devel <xen-devel@lists.xensource.com>, Keir Fraser < Keir.Fraser@cl.cam.ac.uk> Stepping through hypercalls (at the source level, not using the trace trap) causes my dom0 to lockup. Might xen be receiving the int3 and not realize whom to forward to? -Kip _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...ll helps. 1) From papers about Xen architecture found at Xen homepage, Xen seemingly intercepts interrupts of Dom1 (paravirtualization). So interrupts occur in Dom1''s context are sent to Xen, and Xen handles them. Is that correct? But then how can Dom1 gets the interrupts? For example if int3 occurs inside Dom1, Xen intercepts int3, but then how debugger (like gdb) can still work in Dom1? Maybe Xen sends that interrupt back to Dom1 after processing it in VMM layer? 2) I have read linux-xen-sparse/arch/i386/kernel/{traps-xen.c,traps.c,vmlinux.lds.S}, and looks like Dom1 still handles in...

...the real domain :) My smb.conf [global] #--authconfig--start-line-- # Generated by authconfig on 2012/11/28 10:16:49 # DO NOT EDIT THIS SECTION (delimited by --start-line--/--end-line--) # Any modification may be deleted or altered by authconfig in future workgroup = XYZ password server = int3.xyz.com realm = XYZ.COM security = ads idmap uid = 5000-10000 idmap gid = 5000-10000 template homedir = /home/%D/%U template shell = /bin/bash winbind use default domain = true winbind offline logon = false #--authconfig--end-line-- winbind enum users = 1 winbind enum gr...

Looks perfect to me! well, a couple of questions: Why a noop, rather than int3/ud2/etc? Might be worth using the existing code that places such an instruction when building at -O0? & you mention that this causes problems on Windows - but ICF done by the Windows linker does not cause such problems? (I'd have thought they'd result in the same situation - two functio...

...the C++ spec (or the LLVM langref) that would indicate that would allow distinct functions to have identical addresses - so should we do something about this in the LLVM backend? add a little padding? a nop instruction? (if we're adding an instruction anyway, perhaps we might as well make it an int3?) (I came across this due to DWARF issues with zero length functions & thinking about if/how this should be supported)

...e instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. PATCH 3 and PATCH 4 supply an interface for userspace to inject trap. PATCH 1: Define new struct hvm_trap and cleanup vmx exception. PATCH 2: Fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Add insle...

...> used for switching back and forth between native and paravirt mode. > ([1] lists some representative numbers of the increased memory > footprint.) > > Mechanism: the patching itself is done using stop_machine(). That is > not ideal -- text_poke_stop_machine() was replaced with INT3+emulation > via text_poke_bp(), but I'm using this to address two issues: > 1) emulation in text_poke() can only easily handle a small set > of instructions and this is problematic for inlined pv-ops (and see > a possible alternatives use-case below.) > 2) paravirt patching m...

...> used for switching back and forth between native and paravirt mode. > ([1] lists some representative numbers of the increased memory > footprint.) > > Mechanism: the patching itself is done using stop_machine(). That is > not ideal -- text_poke_stop_machine() was replaced with INT3+emulation > via text_poke_bp(), but I'm using this to address two issues: > 1) emulation in text_poke() can only easily handle a small set > of instructions and this is problematic for inlined pv-ops (and see > a possible alternatives use-case below.) > 2) paravirt patching m...

Hi Devs, Consider below testcase. $cat test.cpp #include <vector> #include<type_traits> typedef int _int4 __attribute__((vector_size(16))); typedef union{ int data[4]; struct {int x, y, z, w;}; _int4 vec; } int4; typedef int4 int3; int main() { static_assert(std::alignment_of<int4>::value <= alignof(max_align_t), "over aligned!"); } $clang++ -m32 error: static_assert failed due to requirement 'std::alignment_of<int4>::value <= alignof(max_align_t)' "over aligned it goes smooth when c...

...nch a program that calls it, on x86_64 linux (Ubuntu 18.04), here's what I see at the stop: Process 130404 stopped * thread #1, name = 'doit', stop reason = signal SIGTRAP frame #0: 0x0000000000400541 doit`do_break at stub.ll:2:1 (lldb) disas doit`do_break: 0x400540 <+0>: int3 -> 0x400541 <+1>: retq (lldb) register read rip rip = 0x0000000000400541 doit`do_break + 1 at stub.ll:2:1 Note that rip is reported as pointing to the next instruction after the int3. If I 'continue' from there, the program continues doing whatever was after the debugtrap....

...mem_access(xch, domain_id, default_access, 0, + xenaccess->domain_info->max_pages); + if ( rc < 0 ) + { + ERROR("Error %d setting all memory to access type %d\n", rc, + default_access); + goto exit; + } if ( int3 ) rc = xc_set_hvm_param(xch, domain_id, HVM_PARAM_MEMORY_EVENT_INT3, HVMPME_mode_sync); else rc = xc_set_hvm_param(xch, domain_id, HVM_PARAM_MEMORY_EVENT_INT3, HVMPME_mode_disabled); + if ( rc < 0 ) + { + ERROR("Error %d setting int3 mem_event\n", rc...

...function(mu1) {(exp(U1)/Usum)*dnorm(mu1- alfz*y$z_a1 -alfp*y$p1)} + arg2<- function(mu2) {(exp(U2)/Usum)*dnorm(mu2- alfz*y$z_a2 -alfp*y$p2)} + arg3<- function(mu3) {(exp(U3)/Usum)*dnorm(mu3- alfz*y$z_a3 -alfp*y$p3)} + int1<- integrate(arg1,-Inf,Inf) + int2<- integrate(arg2,-Inf,Inf) + int3<- integrate(arg3,-Inf,Inf) + logl<-sum(y$Ch1*int1$value+ y$Ch2*int2$value + y$Ch3*int3$value) + return(-logl) + } > > p<-optim(c(0,0,0,0,0,0,0,0,0),mnl.lik,y=DATA,method="BFGS",hessian=T) Error in integrate(arg1, -Inf, Inf) : evaluation of function gave a result of wrong...

...S_TF ) { __restore_debug_registers(curr); @@ -1379,9 +1372,11 @@ void vmx_inject_hw_exception(int trap, i domain_pause_for_debugger(); return; } - - type = X86_EVENTTYPE_SW_EXCEPTION; - __vmwrite(VM_ENTRY_INSTRUCTION_LEN, 1); /* int3 */ + if ( trap == TRAP_int3 ) + { + type = X86_EVENTTYPE_SW_EXCEPTION; + __vmwrite(VM_ENTRY_INSTRUCTION_LEN, 1); + } } if ( unlikely(intr_info & INTR_INFO_VALID_MASK) && Attached is the patch I am using. -Stefan -------------- next...

...ed long msr, unsigned long value) +{ + hvm_memory_event_traps(current->domain->arch.hvm_domain + .params[HVM_PARAM_MEMORY_EVENT_MSR], + MEM_EVENT_REASON_MSR, + value, ~value, 1, msr); +} + int hvm_memory_event_int3(unsigned long gla) { uint32_t pfec = PFEC_page_present; diff -r b04de677de31 -r e33d3d37dfbf xen/include/asm-x86/hvm/hvm.h --- a/xen/include/asm-x86/hvm/hvm.h Tue Dec 18 18:16:52 2012 +0000 +++ b/xen/include/asm-x86/hvm/hvm.h Thu Dec 20 14:52:52 2012 +0200 @@ -448,6 +448,7 @@ int hvm_x2apic_...

The enclosed patch adds a llvm.x86.int(i8) intrinsic expanding to the INT or INT3 instruction as appropriate. I haven't yet figured out the best way to select for the INTO instruction across basic blocks (hints would be welcome), but that can be added later with no changes in semantics. -Peter- On Aug 9, 2010, at 6:05 PM, Chris Lattner wrote: > After chatting on IRC, P...

...p;cpuid[3]); mtrr = !!(cpuid[3] & cpufeat_mask(X86_FEATURE_MTRR)); + hvm_memory_event_msr(msr, msr_content); + switch ( msr ) { case MSR_EFER: @@ -3862,6 +3864,7 @@ long do_hvm_op(unsigned long op, XEN_GUE break; case HVM_PARAM_MEMORY_EVENT_INT3: case HVM_PARAM_MEMORY_EVENT_SINGLE_STEP: + case HVM_PARAM_MEMORY_EVENT_MSR: if ( d == current->domain ) { rc = -EPERM; @@ -4485,6 +4488,14 @@ void hvm_memory_event_cr4(unsigned long value...

...-p/lamda) * j * choose(n,j) * (pweibull(x2,shape=p,scale=lamda))^(j-1) * (1 - pweibull(x2,shape=p,scale=lamda))^(n-j) * dweibull(x2,shape=p,scale=lamda) int_2 } v2[j]<-integrate(int2,lower=0,upper=t)$value } sum(v2) } #calculation for t3 fb3<-function(t,r){ v3<-numeric(0) for(j in 1:r){ int3<-function(x3){ int_3<- (p/lamda)^2 * j * choose(n,j) * (pweibull(x3,shape=p,scale=lamda))^(j-1) * (1 - pweibull(x3,shape=p,scale=lamda))^(n-j) * dweibull(x3,shape=p,scale=lamda) int_3 } v3[j]<-integrate(int3,lower=0,upper=t)$value } sum(v3) } a<-c(fb1(t,r),fb2(t,r),fb2(t,r),fb3(t,r)) A...

...hat >> would indicate that would allow distinct functions to have identical >> addresses - so should we do something about this in the LLVM backend? >> add a little padding? a nop instruction? (if we're adding an >> instruction anyway, perhaps we might as well make it an int3?) >> >> (I came across this due to DWARF issues with zero length functions & >> thinking about if/how this should be supported) > > > Yes, I think at least if the optimizer turns a non-empty function into an empty function, What about functions that are already empty...