search for: instructioninfo

...X86Subtarget &Subtarget, SelectionDAG &DAG) { //dont know the details of this part but here i plan to encode 2048 elements again in 32 v64i32 but with different instruction name like previously it was load<LD256; i intend to make it load<LD256_N so that in instructioninfo.td while pattern matching both LD256 and LD256_N are treated separately. 1 will use Reg_B registers and other will use Reg_A respectively. Is it fine??? Please guide me... I need serious help, please..... Thank You On Mon, Jul 10, 2017 at 9:29 AM, hameeza ahmed <hahmed2305 at gmail.com>...

...R_0_V_2 Here i dont want the above to happen rather it should increment R instead of V in this case. It should do something as follows: 1st load to take place in R_0_V_0 2nd load to take place in R_1_V_0 3rd load to take place in R_2_V_0 Now, how to achieve this? Can i mention some condition in instructioninfo.td file? and in registerinfo.td file instead of 1 object Reg_A, there will be 2 objects Reg_A and Reg_B where Reg_B defines same registers but in different order. Reg_B; R_0_V_0, R_1_V_0, R_2_V_0, //here R changes R_0_V_1, R_1_V_1, R_2_V_1, R_0_V_2, R_1_V_2, R_2_V_2, R_0_V_3, R_1_V_3, R_2_V_3....

...ackend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate. Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM source code? (I was looking for it but couldn't find it) Thanks, Artur -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091006/eec456ae/attachment.html>

I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both debugging and fixing this problem, and would appreciate any advice or help anyone can give. I'm unsure if it's actually relevant, but the particular MachineInstr that is involved when the assertion is thrown is always a LDrli (load from an a...

I have defined the intrinsic as * def int_loop: Intrinsic<[],[llvm_i8_ty, llvm_empty_ty],[]>;* and also got the Codegen backend support in Instructioninfo.td file. Then created a .ll file to test it. The .ll file is like this *declare void @llvm.loop(i8, label)define void @fn() nounwind readnone {entry: ..... ..... call void @llvm.loop(i8 10, label %entry) ret void}* But when I run it with llc, I get the following error message Intri...

...efined > paired registers for 64bit operations, however to set a 64bit paired > register with 64bit immediate I have to set each register in that > pair separately with the higher and the lower 32bits of the immediate. > Could anyone give me an advice how to describe it in > *InstructionInfo.td or point me to something similar in the LLVM > source code? (I was looking for it but couldn't find it) > > Thanks, > Artur > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > ht...

...n.mcgruer at gmail.com> > wrote: > > I have a target backend which is currently causing live interval analysis > to throw 'Interval not live at use' errors for many of my benchmarks. I > imagine that this is caused by missing information for my target (probably > in the instructioninfo tablegen?), but I am having difficulties in both > debugging and fixing this problem, and would appreciate any advice or help > anyone can give. > > > Probably, -verify-machineinstrs will tell you what's wrong. > > /jakob > > -------------- next part -------------- An...

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

...ephen McGruer <stephen.mcgruer at gmail.com> wrote: > I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both debugging and fixing this problem, and would appreciate any advice or help anyone can give. Probably, -verify-machineinstrs will tell you what's wrong. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: <...

ok i have managed to compile using lli (jit) as follows: but i dont get assembly file? my sum-main.c file is: #include <stdio.h> #include<stdlib.h> int sum(int a, int b) { return a + b; } int main(int argc, char** argv) { printf("sum: %d\n", sum(atoi(argv[1]), atoi(argv[2])) + sum(atoi(argv[1]), atoi(argv[2]))); return 0; } and i used the following steps to compile. clang

...>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>> I made your mentioned changes and included broadcast >>>>>>>>>>>>>>>>>>> instruction in instructioninfo.td. but i made no >>>>>>>>>>>>>>>>>>> changes in isellowering.cpp file. >>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>> Still getting th...

...;>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>> I made your mentioned changes and included broadcast >>>>>>>>>>>>>>>>>>>>> instruction in instructioninfo.td. but i made no >>>>>>>>>>>>>>>>>>>>> changes in isellowering.cpp file. >>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>&...

...;>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>> I made your mentioned changes and included >>>>>>>>>>>>>>>>>>>>>>>>> broadcast instruction in instructioninfo.td. but >>>>>>>>>>>>>>>>>>>>>>>>> i made no changes in isellowering.cpp file. >>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>&...