Displaying 20 results from an estimated 63 matches for "instritinclass".
2011 Nov 29
2
[LLVMdev] Querying instruction classes
I'd appreciate some help in figuring out how to determine which
InstrItinClass an instruction belongs to.
For example, an InstrItinClass is defined in Schedule.td as:
def FOO : InstrItinClass;
Which is then used to build an InstrItinData in ProcessorItineraries and
to specify the class of a particular instruction.
I'd like to find out from a given instruction which c...
2011 Nov 29
0
[LLVMdev] Querying instruction classes
Hello,
I believe MCInstrDesc::getSchedClass() is what you're looking for.
-Jim
On Nov 28, 2011, at 5:03 PM, Evandro Menezes wrote:
> I'd appreciate some help in figuring out how to determine which
> InstrItinClass an instruction belongs to.
>
> For example, an InstrItinClass is defined in Schedule.td as:
>
> def FOO : InstrItinClass;
>
> Which is then used to build an InstrItinData in ProcessorItineraries and
> to specify the class of a particular instruction.
>
> I'd like...
2016 Dec 03
2
Immediate operand for vector instructions
...A vector instructions
for the Mips back end):
class MSA_I16_FMT<bits<9> opcode>: MSAInst {
bits<16> s16;
let Inst{31-23} = opcode;
let Inst{26-11} = s16;
}
class REP_1R_DESC_BASE<,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
/* From include/llvm/Target/Target.td:
let OperandType = "OPERAND_IMMEDIATE" in {
...
def i64imm : Operand<i64>; */
dag InOperandList = (ins i64imm:$imm...
2016 Mar 18
2
Immediate operand for load instruction, in back end
...t?
Here, the load class has $addrsrc which is a relative address with base a certain
register and offset:
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa,
ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addrsrc);
string AsmString = !strconcat("mov $wd, ($addrsrc)");
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
InstrItinClass Itinerary = itin;...
2012 Jul 03
3
[LLVMdev] bug in tablegen?
...erandList, I.InOperandList
>>
>> But instead, I must back substitute what I know the values of these are.
>> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)
>>
>>
>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
>> InstrItinClass itin> :
>> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,
>> CPU16Regs:$ry),
>> !strconcat(asmstr, "\t$rz, $rx, $ry"),
>> pattern, itin>;
>>
>> class ArithLogicR16<FRRR16_ins I, SDNod...
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...ple,
1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
Okay, so rA, rS, and rB are register operands.
The TableGen classes are defined as:
315 class XForm_base_r3xo_swapped
316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
317 InstrItinClass itin>
318 : I<opcode, OOL, IOL, asmstr, itin> {
319 bits<5> A;
320 bits<5> RST;
321 bits<5> B;
322
323 bit RC = 0; // set by isDOT
324
325 let Inst{6-10} = RST;
326 let Inst{11-15} = A;
327 let Inst{16-20} = B;
328 let Inst{21-30} = xo;
329 let In...
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> : // ...
This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what yo...
2016 May 04
4
Conditional tablegen expressions with math ops?
...a register is
in is just: r%4
Which brings me to tablegen:
We've got this in our specialized ArchInstrInfo.td:
// r1 = r2 op r3
//
class ArithOp_RR< bits<7> op,
string instr_asm,
SDNode opNode,
OperandInfo info,
InstrItinClass itin >
: FR3< op,
(outs info.regClass:$r1),
(ins info.regClass:$r2, info.regClass:$r3),
instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr,
[(set info.regClass:$r1, (opNode info.regClass:$r2,
info.regClass:$r3))],
itin > {
let isF...
2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
...separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);
string AsmString = !strconcat("LS[$addrdst] = $wd;",
instr_asm);
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd...
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...>
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string
> asmstr,
> > 317 InstrItinClass itin>
> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
> > 319 bits<5> A;
> > 320 bits<5> RST;
> > 321 bits<5> B;
> > 322
> > 323 bit RC = 0; // set by isDOT
> >
> > 324
> > 325 let Inst{6-10} = RST;
>...
2012 Jul 05
2
[LLVMdev] bug in tablegen?
...t;;
I think that the problem has to do with the operaand lists not working
if there is substitution
required.
Tablegen is only complaining about $rx, $ry and $rz .
On 07/03/2012 05:35 PM, Sean Silva wrote:
> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
> InstrItinClass itin> : // ...
>
> This class has template args. You don't specify them in the first
> template arg of
> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
>
> --Sean Silva
>
> On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips...
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST: InstrItinClass;
def ALU1: ProcResource<1>;
def ALU2: ProcResource<1>;
def WriteALU1: SchedWriteRes<[ALU1]> { let Lat...
2012 Jul 24
0
[LLVMdev] Instruction Encodings in TableGen
...$rA, (and GPRC:$rS, GPRC:$rB))]>;
>
> Okay, so rA, rS, and rB are register operands.
>
> The TableGen classes are defined as:
>
> 315 class XForm_base_r3xo_swapped
> 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
> 317 InstrItinClass itin>
> 318 : I<opcode, OOL, IOL, asmstr, itin> {
> 319 bits<5> A;
> 320 bits<5> RST;
> 321 bits<5> B;
> 322
> 323 bit RC = 0; // set by isDOT
>
> 324
> 325 let Inst{6-10} = RST;
> 326 let Inst{11-15} = A;
> 327 let In...
2012 Jul 25
2
[LLVMdev] Instruction Encodings in TableGen
...rS, and rB are register operands.
>> >
>> > The TableGen classes are defined as:
>> >
>> > 315 class XForm_base_r3xo_swapped
>> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string
>> asmstr,
>> > 317 InstrItinClass itin>
>> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
>> > 319 bits<5> A;
>> > 320 bits<5> RST;
>> > 321 bits<5> B;
>> > 322
>> > 323 bit RC = 0; // set by isDOT
>> >
>> > 324
>> >...
2008 Aug 22
3
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
...PowerPC/PPCInstrFormats.td (revision 54985)
> +++ lib/Target/PowerPC/PPCInstrFormats.td (working copy)
> @@ -309,6 +309,17 @@
> let Inst{31} = 0;
> }
>
> +class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
> + string asmstr, InstrItinClass itin, list<dag> pattern>
> + : I<opcode, OOL, IOL, asmstr, itin> {
> + let Pattern = pattern;
> + let Inst{6-10} = 0;
> + let Inst{11-15} = 0;
> + let Inst{16-20} = 0;
> + let Inst{21-30} = xo;
> + let Inst{31} = 0;
> +}
> +
> class XForm_25...
2012 Jul 25
0
[LLVMdev] Instruction Encodings in TableGen
...> >
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
> > 317 InstrItinClass itin>
> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
> > 319 bits<5> A;
> > 320 bits<5> RST;
> > 321 bits<5> B;
> > 322
> > 323 bit RC = 0; // set by isDOT
> >
> > 324
> > 325 let Inst{6-10} = RST;
>...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...a separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);
string AsmString = !strconcat("LS[$addrdst] = $wd;",
instr_asm);
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd...
2012 Jul 05
0
[LLVMdev] bug in tablegen?
...do with the operaand lists not working
> if there is substitution
> required.
>
> Tablegen is only complaining about $rx, $ry and $rz .
>
> On 07/03/2012 05:35 PM, Sean Silva wrote:
>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
>> InstrItinClass itin> : // ...
>>
>> This class has template args. You don't specify them in the first
>> template arg of
>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
>>
>> --Sean Silva
>>
>> On Tue, Jul 3, 2012 at 2:29 P...
2012 Jul 03
2
[LLVMdev] bug in tablegen?
...problem is that I should be able to pass parameters:
I.OutOperandList, I.InOperandList
But instead, I must back substitute what I know the values of these are.
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> :
FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,
CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $rx, $ry"),
pattern, itin>;
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
FRRR16<I.f, (outs CP...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...smOperand;
}
class LD_INDIRECT_DESC_BASE2<string instr_asm,
ValueType TyNode,
RegisterOperand ROWD,
RegisterOperand ROWSI = ROWD,
RegisterOperand ROWSP = ROWD, // passthru register
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, ROWSI:$wsptr, ROWSI:$wsi);
string AsmString = "$wd = LS[R($wsi )];";
list<dag> Pattern = [(set ROWD:$wd, (TyNode (masked_gather ROWSP:$wsp,...