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> On Mar 26, 2018, at 5:18 AM, Pedro Lopes via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. > > Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): > > // This section contains legacy support for itineraries. This is > // required until SD and PostRA schedulers are replaced by MachineScheduler....

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required until SD and PostRA schedulers are replaced by MachineScheduler. This poses several ques...

...Pedro Lopes via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > From what I can understand from analyzing several *.td files, there are > two ways of specifying scheduling information for a specific target, either > using SchedWriteRes and InstrItinClass/Data. > > > > Specifically looking at ARMScheduleA9.td, I can find both > representations and a comment (in the beggining of the file): > > > > // This section contains legacy support for itineraries. This is > > // required until SD and PostRA schedulers are r...

...the following function: // reserveResources - Reserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); unsigned FuncUnits = IS->getUnits(); UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits); ReadTable(CurrentState); assert(CachedTable.count(StateTrans) != 0); CurrentState = CachedTable[StateTrans]; } This happens at the packetization stage, i.e. sc...

...if (CPUName.empty()) @@ -42,6 +60,8 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, // Parse features string. ParseSubtargetFeatures(CPUName, FS); + PreviousInMips16Mode = InMips16Mode; + // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); @@ -72,3 +92,45 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass); return OptLevel >= CodeGenOpt::Aggressive; } +void MipsSubtarget::resetSubtarget...

On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for

...----------------------------------------------------------------------===// > + > +#ifndef _AMDGPUSUBTARGET_H_ > +#define _AMDGPUSUBTARGET_H_ > +#include "AMDILSubtarget.h" > + > +namespace llvm { > + > +class AMDGPUSubtarget : public AMDILSubtarget > +{ > + InstrItineraryData InstrItins; > + > +public: > + AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : > + AMDILSubtarget(TT, CPU, FS) > + { > + InstrItins = getInstrItineraryForCPU(CPU); > + } > + > + const InstrItineraryData &getInstrItineraryData() const {...

...exceeds def-use latency. VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); if (DefI == VRegDefs.end()) VRegDefs.insert(VReg2SUnit(Reg, SU)); else { SUnit *DefSU = DefI->SU; if (DefSU != SU && DefSU != &ExitSU) { unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx, DefSU->getInstr()); DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg)); } DefI->SU = SU; } } So if this early exit is taken: // SSA defs do not have output/anti dependencies. // The current operand...

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

.../CodeGen/MachineBasicBlock.h" >> #include "llvm/ADT/DenseMap.h" >> +#include<map> >> >> namespace llvm { >> >> @@ -36,7 +37,7 @@ class MachineInstr; >> class MachineLoopInfo; >> class MachineDominatorTree; >> class InstrItineraryData; >> -class ScheduleDAGInstrs; >> +class DefaultVLIWScheduler; >> class SUnit; >> >> class DFAPacketizer { >> @@ -77,6 +78,8 @@ public: >> // reserveResources - Reserve the resources occupied by a machine >> // instruction and chan...