Displaying 10 results from an estimated 10 matches for "instritins".
2018 Apr 06
0
InstrItin and SchedWriteRes
> On Mar 26, 2018, at 5:18 AM, Pedro Lopes via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi,
>
> From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data.
>
> Specifically looking at ARMScheduleA9.td, I can find both
2018 Mar 26
2
InstrItin and SchedWriteRes
Hi,
>From what I can understand from analyzing several *.td files, there are two
ways of specifying scheduling information for a specific target, either
using SchedWriteRes and InstrItinClass/Data.
Specifically looking at ARMScheduleA9.td, I can find both representations
and a comment (in the beggining of the file):
// This section contains legacy support for itineraries. This is
// required
2018 Apr 06
1
InstrItin and SchedWriteRes
Hello Andy,
I want to use the existing scheduling models to estimate performance on a
subtarget. For that, I am looking at the new llvm-mca tool where they only
use SchedReadWrite and state that not supporting Instruction Itineraries is
a limitation.
I have also read that the Instruction Itineraries allow to model certain
things which cannot be represented in the SchedReadWrite however, I am
2015 Nov 16
2
DFAPacketizer assert failure
...the following function:
// reserveResources - Reserve the resources occupied by a MCInstrDesc and
// change the current state to reflect that change.
void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
unsigned FuncUnits = IS->getUnits();
UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
ReadTable(CurrentState);
assert(CachedTable.count(StateTrans) != 0);
CurrentState = CachedTable[StateTrans];
}
This happens at the packetization stage, i.e. sch...
2013 Apr 01
0
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
...if (CPUName.empty())
@@ -42,6 +60,8 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
+ PreviousInMips16Mode = InMips16Mode;
+
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
@@ -72,3 +92,45 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass);
return OptLevel >= CodeGenOpt::Aggressive;
}
+void MipsSubtarget::resetSubtarget(...
2013 Apr 01
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote:
> IMHO the right way to handle target function attributes is to
> re-initialize the target machine and TTI for every function (if the
> attributes changed). Do you have another solution in mind ?
I don't really understand this.
TargetMachine and TTI may be quite expensive to initialize. Doing so for
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...---------------------------------------------------===//
> +
> +#ifndef _AMDGPUSUBTARGET_H_
> +#define _AMDGPUSUBTARGET_H_
> +#include "AMDILSubtarget.h"
> +
> +namespace llvm {
> +
> +class AMDGPUSubtarget : public AMDILSubtarget
> +{
> + InstrItineraryData InstrItins;
> +
> +public:
> + AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
> + AMDILSubtarget(TT, CPU, FS)
> + {
> + InstrItins = getInstrItineraryForCPU(CPU);
> + }
> +
> + const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...exceeds def-use latency.
VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
if (DefI == VRegDefs.end())
VRegDefs.insert(VReg2SUnit(Reg, SU));
else {
SUnit *DefSU = DefI->SU;
if (DefSU != SU && DefSU != &ExitSU) {
unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
DefSU->getInstr());
DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
}
DefI->SU = SU;
}
}
So if this early exit is taken:
// SSA defs do not have output/anti dependencies.
// The current operand i...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...; @@ -77,6 +78,8 @@ public:
>> // reserveResources - Reserve the resources occupied by a machine
>> // instruction and change the current state to reflect that change.
>> void reserveResources(llvm::MachineInstr *MI);
>> +
>> + const InstrItineraryData *getInstrItins() const { return InstrItins; }
>> };
>>
>> // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
>> @@ -87,20 +90,21 @@ public:
>> // and machine resource is marked as taken. If any dependency is found, a target
>> // API call is made...