Displaying 2 results from an estimated 2 matches for "instrb".
Did you mean:
instr
2016 May 03
9
[Bug 95251] New: vdpau decoder capabilities: not supported
https://bugs.freedesktop.org/show_bug.cgi?id=95251
Bug ID: 95251
Summary: vdpau decoder capabilities: not supported
Product: Mesa
Version: 11.2
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: Drivers/DRI/nouveau
Assignee: nouveau at
2013 Nov 22
1
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
Hi, LLVM list,
I am using Post-RA scheduler to reorder instructions. by now, it's helpful
for our processor but I meet a trouble. In our ISA, we have fixed
instruction pairs. that is to say, our cpu must see instrA right before
instrB. it's not acceptable to have any instruction between them. we call
it an instruction pair.
The problem is I am not aware of describing this kind of constraint in TD
or cpp code. Post-RA scheduler may insert an instruction between
instruction pair. Does any other ISA have similar constraints an...