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Thank you! I wanted to use the right part of the instruction , %a = alloca i32, align 4 - %a here , but I don't quite understand the difference between Instruction object and Value object of a, which is used further , and in this case : %1 = alloca i32, align 4 - I also wanted to use %1 and in this case the only possibility is Instruction object. 2017-07-20 15:32 GMT+02:00 Evgeny Astigeevich

...gt; operand to instructions. In API there is no such thing as the named right > part. An instruction itself is a value which is produced as result of > execution of the instruction. Look at the example: > > > Instr 1: add i32 1, 2 > > > > Instr 2: add i32 <result of Instr1>, 10 > > > We have a def-use connection between Instr 2 and Instr 1. We don't need > names. We can traverse def-use connection in this way ( > http://www.llvm.org/docs/ProgrammersManual.html#helpful-hints-for-common- > operations): > > > Instruction *pi = ...; >...

...ub-registers are spilled and restored > that is related to the changes I made in r192119. > > Suppose I have the following piece of code with four > instructions. %vreg0 and %vreg1 consist of two sub-registers indexed > by sub_lo and sub_hi. > > instr0 %vreg0<def> > instr1 %vreg1:sub_lo<def,read-undef> > instr2 %vreg0<use> > instr3 %vreg1:sub_hi<def> > > If register allocator decides to insert spill and restore instructions > for %vreg0, will it spill the whole register that includes > sub-registers lo and hi? > > instr0 %v...

...sub-registers are spilled and restored > that is related to the changes I made in r192119. > > Suppose I have the following piece of code with four > instructions. %vreg0 and %vreg1 consist of two sub-registers indexed by > sub_lo and sub_hi. > > instr0 %vreg0<def> > instr1 %vreg1:sub_lo<def,read-undef> > instr2 %vreg0<use> > instr3 %vreg1:sub_hi<def> > > If register allocator decides to insert spill and restore instructions > for %vreg0, will it spill the whole register that includes sub-registers lo > and hi? > > instr0...

...egisters are spilled and restored that is related to the changes I made in r192119. >> >> Suppose I have the following piece of code with four instructions. %vreg0 and %vreg1 consist of two sub-registers indexed by sub_lo and sub_hi. >> >> instr0 %vreg0<def> >> instr1 %vreg1:sub_lo<def,read-undef> >> instr2 %vreg0<use> >> instr3 %vreg1:sub_hi<def> >> >> If register allocator decides to insert spill and restore instructions for %vreg0, will it spill the whole register that includes sub-registers lo and hi? >> >...

I've been working on patches to improve subregister liveness tracking on llvm and I wanted to inform the llvm community about the overal design/motivation for them. I will send the patches to llvm-commits later today. Greetings Matthias Braun Subregisters in llvm ==================== Some targets can access registers in different ways resulting in wider or narrower accesses. For