search for: instptx

Displaying 14 results from an estimated 14 matches for "instptx".

2011 Oct 07
6
[LLVMdev] Enhancing TableGen
...or-loop construct that can create them. I think this > was the primary motivation behind Che-Liang's proposal. Ok. We agree here. > I do NOT want to factor out redundancy from instruction definitions like this: > > multiclass PTX_FLOAT_3OP<string opcstr> { > def rr32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, RegF32:$b), > !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; > def ri32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, f32imm:$b), >...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...could be mitigated somewhat by doing something like this: > > class binary_pattern<string opcstr, string type> { > string pattern = !strconcat(opcstr, "$r."#type#"\t$d, $a, $b"); > } > > multiclass PTX_FLOAT_3OP<string opcstr> { > def rr32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, RegF32:$b), > binary_pattern<opcstrm "f32">.pattern, []>; > def ri32 : InstPTX<(outs RegF32:$d), > (ins RndMode:$r, RegF32:$a, f32imm:$b), >...
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
...tions have no value, and I would welcome a for-loop construct that can create them. I think this was the primary motivation behind Che-Liang's proposal. I do NOT want to factor out redundancy from instruction definitions like this: multiclass PTX_FLOAT_3OP<string opcstr> { def rr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, RegF32:$b), !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>; def ri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a, f32imm:$b), !strconcat(o...
2011 Oct 07
6
[LLVMdev] Enhancing TableGen
Evan Cheng <evan.cheng at apple.com> writes: > David, we cannot accept the 'multidef' keyword. Please revert it. Working on it now. > We appreciate you thinking ahead about MIC, but we are against the > massive refactoring and complicated abstraction scheme. We'll never > accept those patches. How about a less massive and complicated scheme? I think we can make
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
...a little bit cognitive cost to understand macro expansion, since it removes a lot of redundancy, I think it is actually more readable. (excerpt of PTXInstrInfo.td) ---------------------------------------- multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { def rrr32 : InstPTX<(outs RegF32:$d), (ins RegF32:$a, RegF32:$b, RegF32:$c), !strconcat(opcstr, ".f32\t$d, $a, $b, $c"), [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a, RegF32:$b),...
2011 Oct 08
3
[LLVMdev] Enhancing TableGen
...at by doing something like this: >> >> class binary_pattern<string opcstr, string type> { >>  string pattern = !strconcat(opcstr, "$r."#type#"\t$d, $a, $b"); >> } >> >> multiclass PTX_FLOAT_3OP<string opcstr> { >>  def rr32 : InstPTX<(outs RegF32:$d), >>                     (ins RndMode:$r, RegF32:$a, RegF32:$b), >>                     binary_pattern<opcstrm "f32">.pattern, []>; >>  def ri32 : InstPTX<(outs RegF32:$d), >>                     (ins RndMode:$r, RegF32:$a, f32imm:$b)...
2011 May 09
3
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
...gt; current PTX_LOGIC version is for 3-operand instructions. A new multiclass > needs to be created for 2-operand logic instructions. I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds : InstPTX<(outs Preds:$d), (ins Preds:$a), !strconcat(opcstr, ".pred\t$d, $a"), [(set Preds:$d, (opnode Preds:$a))]>; ... } But the error is still the same. Where else should I look into? Thanks. Regards, chenwj -- Wei...
2011 May 08
0
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
On Sun, May 8, 2011 at 2:41 AM, 陳韋任 <chenwj at iis.sinica.edu.tw> wrote: > Hi, all > > I am trying to add "not" instruction support to PTX backend. > I add the line below in PTXInstrInfo.td, > > defm NOT : PTX_LOGIC<"not", not>; > > But I get errors below, > > >
2011 May 09
0
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
...needs to be created for 2-operand logic instructions. </pre> </blockquote> <pre wrap=""><!----> I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds : InstPTX<(outs Preds:$d), (ins Preds:$a), !strconcat(opcstr, ".pred\t$d, $a"), [(set Preds:$d, (opnode Preds:$a))]>; ... } </pre> </blockquote> The error here is due to the fact that the 'not' dag is defi...
2011 May 08
2
[LLVMdev] [LLVMDev] Add not instruction to PTX backend
Hi, all I am trying to add "not" instruction support to PTX backend. I add the line below in PTXInstrInfo.td, defm NOT : PTX_LOGIC<"not", not>; But I get errors below, ------------------------------------------------------------------------------- Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is
2011 Oct 06
0
[LLVMdev] TableGen and Greenspun
Jakob Stoklund Olesen <jolesen at apple.com> writes: > The TableGen language seems to be growing Lisp macros from two > different directions. > > Che-Liang Chiou added a preprocessor with for loops, and David Greene > added multidefs. > > It seems that some kind of macro facility is needed, perhaps we should > discuss what it is supposed to look like? Don't
2011 Oct 06
3
[LLVMdev] TableGen and Greenspun
The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob
2011 Oct 06
4
[LLVMdev] TableGen and Greenspun
...multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { for nbit = [32, 32, 64, 64], op_suffix = [r, i, r, i], op_type = [RegF32, f32imm, RegF64, f64imm], op_node_type = [RegF32, fpimm, RegF64, fpimm] in { def rr#op_suffix#nbit : InstPTX<(outs RegF#nbit:$d), (ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c), !strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"), [(set RegF#nbit:$d, (opnode2 (opnode1 RegF#nbit:$a, RegF#nbit:$b), #op_node_...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
...multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> { for nbit = [32, 32, 64, 64], op_suffix = [r, i, r, i], op_type = [RegF32, f32imm, RegF64, f64imm], op_node_type = [RegF32, fpimm, RegF64, fpimm] in { def rr#op_suffix#nbit : InstPTX<(outs RegF#nbit:$d), (ins RegF#nbit:$a, RegF#nbit:$b, #op_type:$c), !strconcat(opcstr, ".f#nbit\t$d, $a, $b, $c"), [(set RegF#nbit:$d, (opnode2 (opnode1 RegF#nbit:$a, RegF#nbit:$b), #op_node_...