search for: implicit_def

Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> => %vreg10<def> = IMPLICIT_D...

...atrik Hägglund ________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jakob Stoklund Olesen Sent: den 9 maj 2012 18:21 To: Jonas Paulsson Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] register allocation problems in trunk with IMPLICIT_DEF On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: Hi, Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: %vreg9<def> = IMPLICIT_DEF %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<...

On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break: > > %vreg9<def> = IMPLICIT_DEF > %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi > %vreg12<def> = sub %vreg10<kill>, %vreg11<kill> > => >...

Guys, I think I figure out the way that the current LLVM allocators are handling IMPLICIT_DEF's. One question more: why are you adding null length intervals to IMPLICIT_DEF instructions? If they were non-null, I think the code to handle them would be more homogeneous, e.g a traversal of the intervals during register allocation would already reveal virtuals defined implicitly. best,...

Hi, I have a MachineInstr that writes to a subreg, but clobbers the superreg. How should I BuildMI this instruction? I try to do a IMPLICIT_DEF super_reg and then write to a subreg of that super register , but it gets DCE:ed. Is there a way to express this clobbering of a superregister? thanks, Jonas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llv...

Hi, guys. sorry if this has already been discussed, but I still feel like clarifying: how should the register allocator handle IMPLICIT_DEF instructions? The LiveIntervalAnalysis class is assigning them zero length intervals. After I removed this, e.g, by removing the lines: if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { DOUT << "is a implicit_def\n"; return; } from LiveIntervalAnalysis, it mak...

Hi, I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture. def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)), (INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOff...

...t; is implicitly defined as FPUabRegisterClass. > > This register class accepts the v2f32 type, but for others addressing > mode context this register should be FPUabOffsetClass. > > Is there a mechanism, an option to inforce/control the RegisterClass of > registers defined by IMPLICIT_DEF ? A virtual register has a specific register class assigned to it, and is implicitly a member of any superclass of that class. If you want to use the register in a place that requires another class, you will need to create a new virtual register for the new class and copy the value into it. In...

I noticed that the AsmWriter backend of TableGen is no longer handling the IMPLICIT_DEF case in printInstruction() function (by calling printImplicitDef). It was doing so in llvm 2.6. Is it supposed to be handled explicitly in printMachineInstruction()? What is the recommended method? Manjunath

Can someone explain where things like IMPLICIT_DEF_FR64 come from? I believe something is noticing a use before def and inserting some kind of bogus code to compensate. The machine instructions look like this (x86): %reg1069<def> = IMPLICIT_DEF_FR64 FsMOVLPDmr %reg0, 1, %reg0, 0, %reg1069 This is no good -- it stores to zero. Thanks....

...for a follow up. We would like to accelerate this follow up, because we obviously want to get our downstream backend working again. One part of this discussion concerned how freeze should behave on MIR level. Especially if there needs to be a MIR FREEZE instruction and whether the semantics of IMPLICIT_DEF need to be changed. In SelectionDAG, FREEZE is currently handled as a simple COPY. This seems to me like SelectionDAG ignores the semantics of FREEZE, since COPY has other semantics? Also, would this be acceptable for the GlobalISel IRTranslator (even if only as a first step)? Best regards, D...

...) && getSubRegisterRegClass(*I, SubIdx) == TRC) return *I; assert(false && "Couldn't find the register class"); return 0; } ----------------------------------------------------------------- The getSubRegisterRegClass uses SubIdx - 1; so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because getSubRegisterRegClass will fail.(GR16_ does not have a SubRegClass at index -1.) OTOH, if you use SubIdx as 1, both in SubRegSet and x86_subreg_8bit, the INSERT_SUBREG (IMPLICIT_DEF, AL, 1) will work. But then INSERT_SUBREG (AX, AH, 2) will not work because getSub...

...// only in OptForSize mode. It eliminates an instruction, but it also > > // eliminates a whole-register clobber (the load), so it introduces a > > // partial register update condition. > > def : Pat<(f32 (fsqrt (load addr:$src))), > > (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>, > > Requires<[HasAVX, OptForSize]>; > > > > This is generated: > > vsqrtss (%rdi), %xmm0, %xmm0 > > > > regardless of whether I specify -Os or -O1 with clang. > > You might want to take a look at the Mips target,...

...> > bb134: > > %reg1645 = 1.0 > > > > bb74: > > %reg1176 = MOVAPS %reg1645 > > %reg1177 = MOVAPS %reg1646 > > [...] > > > > bb108: > > %reg1645 = <expr> > > %reg1646 = %reg1176 > > I find it a little strange that the IMPLICIT_DEF disappears. Besides > that, it looks okay up to here. I just verified that it does disappear. > > Should llvm be able to handle situations like > > this or is the result undefined? > > LLVM should be able to handle the IL in question, I think. Using > undef in the way th...

....g. i8. > > > > > Can I use to set a superreg of i16 type with two i8 values, and use > > the supperreg as an operand somewhere else? > > > Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The > way to do it is: > > > v4 = insert_subreg implicit_def, v1, 0 > v3 = insert_subreg v4, v2, 1 > > > Evan > This is how my register classes look like: def FSR0L : Register<"FSR0L">; def FSR0H : Register<"FSR0H">; def FSR1L : Register<"FSR1L">; def FSR1H : Regis...

...g1645 = 1.0 >>> >>> bb74: >>> %reg1176 = MOVAPS %reg1645 >>> %reg1177 = MOVAPS %reg1646 >>> [...] >>> >>> bb108: >>> %reg1645 = <expr> >>> %reg1646 = %reg1176 >> >> I find it a little strange that the IMPLICIT_DEF disappears. Besides >> that, it looks okay up to here. > > I just verified that it does disappear. It's intentional. We don't want a live interval defined by an implicit_def. It unnecessarily increases register pressure. Evan > > >>> Should llvm be able to h...

...2_loadruh_io undef %r0, 0 >> J2_jump %bb.tail >> >> bb.2: >> J2_jump %bb.tail >> >> bb.tail: >> liveins: %r0 >> PS_storerhabs 0, killed %r0 >> J2_jump %bb.3, implicit-def %pc >> >> Then we could insert IMPLICIT_DEF into bb.2 and everything would be fine. This is not what happens, though. In this case, the entire bb.2 will be used as the new tail leaving us without a good point to put the implicit def at. > > We should need to put the implicit_def only if the related register is dead (as in not live-out...

...R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; > > > class GR16_ ..... { > let SubRegClassList = [GR8]; > } Right. Subreg index starts from 1. This ought to be fixed but it's not (yet). > > > The getSubRegisterRegClass uses SubIdx - 1; > > so INSERT_SUBREG (IMPLICIT_DEF, AL, 0) will not work, because > getSubRegisterRegClass will fail.(GR16_ does not have a SubRegClass > at index -1.) > > OTOH, if you use SubIdx as 1, both in SubRegSet and x86_subreg_8bit, > the INSERT_SUBREG (IMPLICIT_DEF, AL, 1) will work. Ok. > > > But then INSER...

...n BB#0 and then > redefined in BB#1. Both definitions can reach the use of R0 in BB#2: > > > *** > Before Hexagon RDF optimizations > # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs > > BB#0: >     Live Ins: %P0 >         %R0<def> = IMPLICIT_DEF >         J2_jumpt %P0, <BB#2>, %PC<imp-def>  ; Conditional branch to BB#2 >     Successors according to CFG: BB#1 BB#2 > > BB#1: >     Predecessors according to CFG: BB#0 >         %R0<def> = IMPLICIT_DEF >     Successors according to CFG: BB#2 > &g...

...gt;> Can I use to set a superreg of i16 type with two i8 values, and use >>> the supperreg as an operand somewhere else? >> >> >> Suppose you want to use a pair of i8 v1, v2 to create a i16 v3. The >> way to do it is: >> >> >> v4 = insert_subreg implicit_def, v1, 0 >> v3 = insert_subreg v4, v2, 1 >> >> >> Evan >> > > This is how my register classes look like: > > def FSR0L : Register<"FSR0L">; > def FSR0H : Register<"FSR0H">; > def FSR1L : Register<&qu...