Displaying 15 results from an estimated 15 matches for "ilopcod".
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ilopcode
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...com>> wrote:
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
>
> What I am trying to do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let AsmString =...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
>
> What I am trying to do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let AsmString =...
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
...RV4I32, OpNode>;
...
}
class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode>
: ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),
"mov $dst, $src0",
[(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");...
2011 Nov 22
2
[LLVMdev] PTX builtin functions.
...VMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>], []>;
This allows us to write a multi-def for int_AMDIL_mad like so:
defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
Where TernaryIntrinsicFloat is defined as:
multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
{
def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
(ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
!strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
[(set GPRF32:$dst,
(intr GPRF32:$src, GPRF32:$src2, GPRF32:$src3))]>;...
2011 Nov 23
2
[LLVMdev] PTX builtin functions.
...VMMatchType<0>], []>;
> >
> > This allows us to write a multi-def for int_AMDIL_mad like so:
> > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
> >
> > Where TernaryIntrinsicFloat is defined as:
> > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
> > {
> > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
> > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
> > !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
> > [(set GPRF32:$dst,
> >...
2011 Nov 23
0
[LLVMdev] PTX builtin functions.
... LLVMMatchType<0>, LLVMMatchType<0>], []>;
>
> This allows us to write a multi-def for int_AMDIL_mad like so:
> defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
>
> Where TernaryIntrinsicFloat is defined as:
> multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
> {
> def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
> (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
> !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
> [(set GPRF32:$dst,
> (intr GPRF32:$src, GPRF32:$s...
2011 Nov 23
0
[LLVMdev] PTX builtin functions.
...> > >
> > > This allows us to write a multi-def for int_AMDIL_mad like so:
> > > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
> > >
> > > Where TernaryIntrinsicFloat is defined as:
> > > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
> > > {
> > > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
> > > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
> > > !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
> > > [(set GPRF3...
2011 Dec 04
2
[LLVMdev] PTX builtin functions.
...> > > This allows us to write a multi-def for int_AMDIL_mad like so:
>> > > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
>> > >
>> > > Where TernaryIntrinsicFloat is defined as:
>> > > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
>> > > {
>> > > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
>> > > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
>> > > !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
>> > &...
2011 Dec 08
3
[LLVMdev] PTX builtin functions.
...> > > This allows us to write a multi-def for int_AMDIL_mad like so:
>> > > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
>> > >
>> > > Where TernaryIntrinsicFloat is defined as:
>> > > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
>> > > {
>> > > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
>> > > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
>> > > !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
>> > &...
2011 Dec 05
0
[LLVMdev] PTX builtin functions.
...allows us to write a multi-def for int_AMDIL_mad like so:
> >> > > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
> >> > >
> >> > > Where TernaryIntrinsicFloat is defined as:
> >> > > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
> >> > > {
> >> > > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
> >> > > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
> >> > > !strconcat(opcode.Text, " $dst, $src, $src2, $src3&quo...
2011 Dec 08
0
[LLVMdev] PTX builtin functions.
...allows us to write a multi-def for int_AMDIL_mad like so:
> >> > > defm MAD : TernaryIntrinsicFloat<IL_OP_MAD, int_AMDIL_mad>;
> >> > >
> >> > > Where TernaryIntrinsicFloat is defined as:
> >> > > multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
> >> > > {
> >> > > def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
> >> > > (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
> >> > > !strconcat(opcode.Text, " $dst, $src, $src2, $src3&quo...
2011 Nov 22
0
[LLVMdev] PTX builtin functions.
On Mon, Nov 21, 2011 at 5:31 PM, Justin Holewinski
<justin.holewinski at gmail.com> wrote:
> On Mon, Nov 21, 2011 at 11:45 AM, Alberto Magni <alberto.magni86 at gmail.com>
> wrote:
>>
>> On Mon, Nov 21, 2011 at 3:36 PM, Justin Holewinski
>> <justin.holewinski at gmail.com> wrote:
>> > On Mon, Nov 21, 2011 at 7:01 AM, Alberto Magni
>> >
2011 Nov 21
2
[LLVMdev] PTX builtin functions.
On Mon, Nov 21, 2011 at 11:45 AM, Alberto Magni
<alberto.magni86 at gmail.com>wrote:
> On Mon, Nov 21, 2011 at 3:36 PM, Justin Holewinski
> <justin.holewinski at gmail.com> wrote:
> > On Mon, Nov 21, 2011 at 7:01 AM, Alberto Magni <
> alberto.magni86 at gmail.com>
> > wrote:
> >>
> >> Hi Justin,
> >>
> >> attached you find